Semiconductor device and method of manufacturing the same

ABSTRACT

There are contained first and second conductive plugs formed in first insulating layer, an island-like oxygen-barrier metal layer for covering the first conductive plug, an oxidation-preventing insulating layer formed on the first insulating layer to cover side surfaces of the oxygen-barrier metal layer, a capacitor having a lower electrode formed on the oxygen-barrier metal layer and the oxidation-preventing insulating layer, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, a second insulating layer for covering the capacitor and the oxidation-preventing insulating layer, a third hole formed in respective layers from the second insulating layer to the oxidation-preventing insulating layer on the second conductive plug, and a third conductive plug formed in the third hole and connected to the second conductive plug.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims priority of JapanesePatent Applications No. 2002-74566, filed on Mar. 18, 2002, No.2002-249448, filed on Aug. 28, 2002, and No. 2003-64601, filed on Mar.11, 2003, the contents being incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and amethod of manufacturing the same and, more particularly, a semiconductordevice having a capacitor and a method of manufacturing the same.

[0004] 2. Description of the Prior Art

[0005] The ferroelectric capacitor of FeRAM (Ferroelectric Random AccessMemory) that is mass-produced currently has the planar structure.

[0006] However, the capacitor having the stacked structure, a cell areaof which can be reduced smaller, is needed in future in reply to therequest for the higher integration. The stacked structure has theconductive plug, which is used to provide contact with the semiconductorsubstrate, directly under the lower electrode of the ferroelectriccapacitor. As set forth in Patent Application Publication (KOKAI)2001-443476, for example, it is normal that tungsten or polysilicon isused as the material of such conductive plug.

[0007] While, the FeRAM and the logic device are hybrid-integrated inmany products. For example, there are the semiconductor chip used in thesecurity field that needs the authentication, the IC card that isutilized gradually in the local self-governing body, etc.

[0008] In the logic semiconductor device, it is common that the processusing the tungsten plug is employed to connect the underlying conductivepattern and the overlying conductive pattern. It is of course that, asthe spice parameter used to design the circuit, the resistance value ofthe tungsten plug is employed.

[0009] Therefore, if the significances to make efficient use ofaccumulated circuit design properties and to lower the developmentman-hour/cost are considered, it has the great merit to use the tungstenplug as the contact plug in the logic hybrid-integrated FeRAM like theprior art.

[0010] Next, steps of forming the memory cell having the stackedcapacitor will be explained hereunder.

[0011] First, steps required until a structure shown in FIG. 1A isformed will be explained hereunder.

[0012] An element isolation insulating film 102 is formed around anelement forming region of a silicon substrate 101, and then a well 103is formed in the element forming region. Then, two MOS transistors 104are formed in one well 103.

[0013] The MOS transistors 104 have gate electrodes 104 b formed on thewell 103 via a gate insulating film 104 a, and impurity diffusionregions 104 c, 104 d formed in the well 103 on both sides of the gateelectrodes 104 b to serve as the source/drain. Also, insulatingsidewalls 105 used to form high concentration impurity regions 104 e inthe impurity diffusion regions 104 c, 104 d are formed on both sidesurfaces of the gate electrodes 104 b.

[0014] Then, a transistor protection insulating film 106 for coveringthe MOS transistors 104 is formed on the silicon substrate 101, and thena first interlayer insulating film 107 is formed on the transistorprotection insulating film 106.

[0015] And, first contact holes 107 a are formed in the first interlayerinsulating film 107 on one impurity diffusion regions 104 c of the MOStransistors 104, and then first contact plugs 108 are buried in thefirst contact holes 107 a.

[0016] Then, a first metal film 109, a ferroelectric film 110, and asecond metal film 111 are formed sequentially on the first contact plugs108 and the first interlayer insulating film 107. As the ferroelectricfilm 110, for example, a PZT film is formed.

[0017] Then, as shown in FIG. 1B, capacitors 112 are formed bypatterning the first metal film 109, the ferroelectric film 110, and thesecond metal film 111 by virtue of the photolithography method.

[0018] In the capacitor 112, a lower electrode 109 a is formed of thefirst metal film 109, a dielectric film 110 a is formed of theferroelectric film 110, and an upper electrode 111 a is formed of thesecond metal film 111. The capacitor is the stacked capacitor, and thelower electrodes 109 a are connected to one impurity diffusion regions104 c of the MOS transistors 104 via the underlying first contact plugs108 respectively.

[0019] Then, as shown in FIG. 1C, a capacitor protection film 113 isformed on the capacitors 112 and the first interlayer insulating film107. Then, a second interlayer insulating film 114 is formed on thecapacitor protection film 113. Then, a second contact hole 114 a isformed on the other impurity diffusion region 104 d of the MOStransistors 104 by patterning the second interlayer insulating film 114,the capacitor protection film 113, the first interlayer insulating film107, and the transistor protection insulating film 106 by virtue of thephotolithography method. Then, a second contact plug 115 is formed inthe second contact hole 114 a.

[0020] Next, steps required until a structure shown in FIG. 1D is formedwill be explained hereunder.

[0021] Third contact holes 114 b are formed on the upper electrodes 110a of the capacitors 112 by patterning the second interlayer insulatingfilm 114 and the capacitor protection film 113. Then, a conductive filmis formed on the second interlayer insulating film 114 and in the thirdcontact holes 114 b, and then this conductive film is patterned. Thus,wirings 116 a connected to the upper electrodes 111 a of the capacitors112 respectively are formed and simultaneously a conductive pad 116 b isformed on the second contact plug 115.

[0022] Then, a third interlayer insulating film 117 is formed on thewirings 116 a, the conductive pad 116 b, and the second interlayerinsulating film 114. Then, a hole 117 a is formed on the conductive pad116 b by patterning the third interlayer insulating film 117. Then, afourth conductive plug 118 is formed in the hole 117 a.

[0023] Then, a bit line 118 connected to the fourth conductive plug 118is formed on the third interlayer insulating film 117.

[0024] As the ferroelectric film 110 of the ferroelectric capacitor 112,for example, the PZT film is formed. After the formation, this PZT filmis annealed in the oxygen atmosphere to crystallize. After the lateretching, the recovery annealing of the PZT film, etc. are carried out inthe oxygen atmosphere.

[0025] Here, the situation in which the tungsten plugs are formed as thecontact plug directly under the ferroelectric capacitors shown in FIGS.1A to 1D will be considered.

[0026] As set forth in Patent Application Publication (KOKAI) Hei10-303398, the tungsten plug is oxidized very quickly at a lowtemperature. Also, oxidation of the tungsten plug spreads throughout theplug once such oxidation occurs, so that the contact failure is causedeasily and reduction in the yield of the FeRAM device is brought about.

[0027] Also, even if the polysilicon is employed as the material of thecontact plug, such polysilicon is also oxidized though the oxidation isnot so serious as the tungsten.

[0028] By the way, as explained above, in order to improve theperformance of the ferroelectric capacitor, the annealing is required invarious oxygen atmospheres.

[0029] Therefore, improvement in the performance of the ferroelectriccapacitor and improvement in the performance of the contact plug were inthe trade-off relationship.

[0030] In contrast, various trials were made to prevent the abnormaloxidation of the tungsten plug in the crystallization annealing of theferroelectric film or in the recovery annealing of the ferroelectriccapacitor. For example, in Patent Application Publication (KOKAI) Hei10-303398, Patent Application Publication (KOKAI) 2000-349255, PatentApplication Publication (KOKAI) 2001-44377, Patent ApplicationPublication (KOKAI) Hei 10-150155, and Patent Application Publication(KOKAI) 2000-349252, the structure in which the oxygen-barrier-metallayer is formed between the capacitor and the tungsten plug is setforth.

[0031] As described above, in the MOS transistor 104 constituting thememory cell, one impurity diffusion region 104 c is connected to theferroelectric capacitor 112 via the contact plug 108, and the otherimpurity diffusion region 104 d is connected to the bit line 119 viaanother contact plug 115.

[0032] The reason why the contact plug 115 for bit-line connection isformed after the ferroelectric capacitor 112 is formed is to prevent theoxidation of the contact plug 115 in the crystallization annealing ofthe ferroelectric film 110 in the oxygen atmosphere or in the recoveryannealing of the ferroelectric capacitor 112.

[0033] However, an aspect ratio of the contact plug 115 for bit-lineconnection is increased more and more with the further miniaturizationin future. Therefore, technical subjects that are to be overcome newlysuch as the etching to form the contact hole 114 a for bit-lineconnection, the filling of the glue layer in the contact hole 114 a forbit-line connection, etc. are brought about.

SUMMARY OF THE INVENTION

[0034] It is an object of the present invention to provide asemiconductor device capable of forming satisfactorily a conductive plugconnected to a capacitor and other conductive plugs, and a method ofmanufacturing the same.

[0035] According to one aspect of the present invention, there isprovided a semiconductor device comprising: a first impurity diffusionregion and a second impurity diffusion region formed on a surface layerof a semiconductor substrate; a first insulating layer formed over thesemiconductor substrate; a first hole and a second hole formed in thefirst insulating layer; a first conductive plug formed in the first holeand connected electrically to the first impurity diffusion region; asecond conductive plug formed in the second hole and connectedelectrically to the second impurity diffusion region; an island-likeoxygen-barrier metal layer formed on the first insulating layer over thefirst conductive plug and its peripheral area; an oxidation preventinglayer formed on the first insulating layer and made of material thatprevents oxidation of the second conductive plug; a capacitor having alower electrode formed on the oxygen-barrier metal layer, a dielectriclayer formed on the lower electrode, and an upper electrode formed onthe dielectric layer; a second insulating layer for covering thecapacitor and the oxidation preventing layer; a third hole formed in thesecond insulating layer on the second conductive plug; and a thirdconductive plug formed in the third hole and connected electrically tothe second conductive plug.

[0036] The above subject is overcome by providing a semiconductor devicemanufacturing method that comprises the steps of forming a firstimpurity diffusion region and a second impurity diffusion region on asurface layer of a semiconductor substrate; forming a first insulatinglayer over the semiconductor substrate; forming a first hole and asecond hole in the first insulating layer; forming a first conductiveplug, which is connected electrically to the first impurity diffusionregion, in the first hole and simultaneously a second conductive plug,which is connected electrically to the second impurity diffusion region,in the second hole; forming an oxygen-barrier metal layer on the firstconductive plug and the second conductive plug and the first insulatinglayer; patterning the oxygen-barrier metal layer to leave theoxygen-barrier metal layer like an island on the first conductive plug;forming an oxidation preventing layer on the first insulating layer overthe second conductive plug and its peripheral area; forming aninsulating adhesion layer on the oxidation preventing layer and theoxygen-barrier metal layer; exposing an upper surface of theoxygen-barrier metal layer by polishing the insulating adhesion layer;forming a first conductive layer on the oxygen-barrier metal layer andthe insulating adhesion layer; forming a dielectric layer on the firstconductive layer; forming a second conductive layer on the dielectriclayer; forming a capacitor on the oxygen-barrier metal layer over thefirst conductive plug by patterning the second conductive layer, thedielectric layer, and the first conductive layer; forming a secondinsulating layer over the capacitor, the insulating adhesion layer, andthe oxidation preventing layer; forming a third hole over the secondconductive plug by patterning the second insulating layer; and forming athird conductive plug, which is connected electrically to the secondconductive plug, in the third hole.

[0037] According to the present invention, the first and secondconductive plugs are formed in the first insulating layer over thesemiconductor substrate, then the oxygen-barrier metal layer is formedon the first conductive plug and the oxidation-preventing insulatinglayer is formed on the second conductive plug, then the capacitor isformed on the first conductive plug via the oxygen-barrier metal layer,then the second insulating layer for covering the capacitor is formed,and then the third conductive plug is formed on the second conductiveplug and in the second insulating layer.

[0038] Therefore, the structure for connecting the impurity diffusionregion and the upper wiring is made on a via-to-via basis, and it is notneeded to form the holes having the large aspect ratio at a time, andthe filling of the holes can be facilitated. As a result, the up-to-dateequipment is not required, and the development cost and the step costcan be reduced.

[0039] Also, the oxygen-barrier metal layer is formed on the firstinsulating layer over the first conductive plug and its peripheral areaout of the first conductive plug and the second conductive plug. Also,the oxidation-preventing insulating layer is formed on the secondconductive plug and the first insulating layer. Therefore, the abnormaloxidation of the first conductive plug is prevented by theoxygen-barrier metal layer, and also the abnormal oxidation of thesecond conductive plug is prevented by the oxidation-preventinginsulating layer. As a result, in the step of growing the insulatingadhesion layer as the underlying layer of the capacitor, the step ofcrystallization annealing of the dielectric layer executed to form thecapacitor on the first conductive plug, and the step of the recoveryannealing after formation of the capacitor, the first and secondconductive plugs are never abnormally oxidized.

[0040] In addition, since the oxygen-barrier metal layer and theinsulating adhesion layer are planarized simultaneously by thepolishing, the capacitor lower electrode formed on the oxygen-barriermetal layer is formed flat. Thus, generation of the degradation of thedielectric layer formed on the lower electrode is avoided, and alsoformation of the capacitor with good characteristics can be formed.

[0041] Also, the third conductive plug is formed in the secondinsulating layer for covering the capacitor to connect the thirdconductive plug and the second conductive plug. Thus, the abnormaloxidation of the second conductive plug can be avoided until the thirdconductive plug is formed after the oxidation-preventing insulatinglayer is formed. In other words, since the oxidation-preventinginsulating layer is present around the second conductive plug, theentering of the oxygen from the upper surface of the interlayerinsulating layer is prevented and thus the oxidation of the secondconductive plug is prevented much more. In this case, since the step ofthe oxygen annealing is not contained in the steps executed from theformation of the first and second conductive plugs to the formation ofthe insulating adhesion layer, the abnormal oxidation of the first andsecond conductive plugs is not caused prior to the formation of theoxidation-preventing insulating layer.

[0042] Further, according to the present invention, the oxygen-barriermetal layer instead of the oxidation-preventing insulating layer isformed like the island on the second conductive plug. Therefore, notonly the same advantages as the oxidation-preventing insulating layer isobtained but also the step of forming the oxidation-preventinginsulating layer is omitted. In this case, the oxygen-barrier metallayer formed like the island on the first and second conductive plugsrespectively can be formed simultaneously, and thus the number of stepsis never increased.

[0043] Also, the oxidation-preventing layer made of the same material asthe oxygen-barrier metal layer is formed on the second conductive plugand its peripheral area and, in addition, side surfaces of theoxygen-barrier metal layer formed on the first and second conductiveplugs respectively are covered with the oxidation-preventing insulatinglayer. Therefore, the oxygen is prevented from entering from theclearance between the oxygen-barrier metal layer and the firstinsulating layer, and also the oxidation of the first and secondconductive plugs is prevented.

[0044] In this case, the step of patterning the lower electrode isreduced, by adopting the oxygen-barrier metal layer formed on the firstconductive plug under the capacitor as the lower electrode.

[0045] The peeling-off of the capacitor lower electrode is prevented, byforming the conductive adhesion layer between the conductive layerconstituting the capacitor lower electrode and the oxygen-barrier metallayer.

[0046] The adherence between the oxygen-barrier metal layer and thefirst insulating layer is improved, by forming the conductive adhesionlayer between the oxygen-barrier metal layer and the first insulatinglayer. Therefore, the oxygen is prevented without fail from beingsupplied from the clearance between the oxygen-barrier metal layer andthe first insulating layer to the conductive plug.

[0047] Further, when the oxygen-barrier metal layer is formed as themulti-layered structure and the upper layer is formed of the materialthat can be relatively easily polished, e.g., iridium oxide, theunderlying layer of the capacitor is formed flatter by polishing theinsulating adhesion layer and the oxygen-barrier metal layer. Therefore,the characteristic of the capacitor is improved.

[0048] In the case that the oxygen-barrier metal layer is patterned byusing the hard mask, the insulating adhesion layer is formed on the hardmask and the oxidation-preventing insulating layer after the patterningof the oxygen-barrier metal layer, and then the insulating adhesionlayer and the hard mask is polished continuously until theoxygen-barrier metal layer is exposed. Therefore, the independent stepof removing the hard mask is omitted. In addition, since the secondconductive plug is covered with the insulating adhesion layer inremoving the hard mask, the damage of the second conductive plug inremoving the hard mask is avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

[0049]FIGS. 1A to 1D are sectional views showing steps of forming thesemiconductor device in the prior art;

[0050]FIGS. 2A to 2O are sectional views showing steps of manufacturinga semiconductor device according to a first embodiment of the presentinvention;

[0051]FIGS. 3A to 3I are sectional views showing steps of manufacturinga semiconductor device according to a second embodiment of the presentinvention;

[0052]FIGS. 4A to 4E are sectional views showing steps of manufacturinga semiconductor device according to a third embodiment of the presentinvention;

[0053]FIGS. 5A to 5G are sectional views showing steps of manufacturinga semiconductor device according to a fourth embodiment of the presentinvention;

[0054]FIG. 6 is a sectional view showing steps of manufacturing anothersemiconductor device according to the fourth embodiment of the presentinvention;

[0055]FIGS. 7A to 7I are sectional views showing steps of manufacturinga semiconductor device according to a fifth embodiment of the presentinvention;

[0056]FIG. 8 is a plan view showing an alignment mark in thesemiconductor wafer;

[0057]FIG. 9 is a plan view showing another alignment mark in thesemiconductor wafer;

[0058]FIGS. 10A to 10I are sectional views showing steps ofmanufacturing a semiconductor device according to a sixth embodiment ofthe present invention;

[0059]FIG. 11 is a sectional view showing another semiconductor deviceaccording to the sixth embodiment of the present invention;

[0060]FIGS. 12A to 12G are sectional views showing steps ofmanufacturing a semiconductor device according to a seventh embodimentof the present invention;

[0061]FIG. 13 is a sectional view showing another semiconductor deviceaccording to the seventh embodiment of the present invention; and

[0062]FIGS. 14A to 14G are sectional views showing steps ofmanufacturing a semiconductor device according to an eighth embodimentof the present invention; and

[0063]FIGS. 15A to 15D are sectional views showing steps ofmanufacturing a semiconductor device according to a ninth embodiment ofthe present invention; and

[0064]FIGS. 16A to 16C are sectional views showing steps ofmanufacturing a semiconductor device in which an interval between thecapacitors is in narrow according to a comparative example; and

[0065]FIG. 17 is a plane view showing memory cell region in asemiconductor device according to embodiment of the present invention;and

[0066]FIGS. 18A to 18G are sectional views showing steps ofmanufacturing a semiconductor device according to a tenth embodiment ofthe present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0067] Embodiments of the present invention will be explained in detailwith reference to the drawings hereinafter.

[0068] (First Embodiment)

[0069]FIGS. 2A to 2O are sectional views showing steps of manufacturinga semiconductor device according to a first embodiment of the presentinvention.

[0070] Next, steps required until a sectional structure shown in FIG. 2Ais formed will be explained hereunder.

[0071] First, an element isolation recess is formed around a transistorforming region of an n-type or p-type silicon (semiconductor) substrate1 by the photolithography method, and then an element isolationinsulating layer 2 is formed by burying silicon oxide (SiO₂) in theelement isolation recess. The element isolation insulating layer 2having such structure is called STI (Shallow Trench Isolation). In thiscase, an insulating layer formed by the LOCOS (Local Oxidation ofSilicon) method may be employed as the element isolation insulatinglayer.

[0072] Then, a p-type well 1 a is formed by introducing the p-typeimpurity selectively into the transistor forming region of the siliconsubstrate 1 in the memory cell region.

[0073] Then, a silicon oxide layer as a gate insulating layer 3 isformed by thermally oxidizing a surface of the p-type well 1 a of thesilicon substrate 1.

[0074] Then, an amorphous silicon or polysilicon layer and a tungstensilicide layer are formed sequentially on an overall upper surface ofthe silicon substrate 1. Then, gate electrodes 4 a, 4 b are formed onthe p-type well 1 a in the memory cell region by patterning the siliconlayer and the tungsten silicide layer by virtue of the photolithographymethod. These gate electrodes 4 a, 4 b are formed on the siliconsubstrate 1 via the gate insulating layer 3.

[0075] In this case, in the memory cell region, two gate electrodes 4 a,4 b are formed on one p-type well 1 a in parallel and these gateelectrodes 4 a, 4 b constitute a part of the word line.

[0076] Then, first to third n-type impurity diffusion regions 5 a to 5 cserving as the source/drain are formed by ion-implanting the n-typeimpurity, e.g., phosphorus, into the p-type well 1 a on both sides ofthe gate electrodes 4 a, 4 b.

[0077] Then, an insulating layer, e.g., a silicon oxide (SiO₂) layer isformed on the overall surface of the silicon substrate 1 by the CVDmethod. Insulating sidewall spacers 6 are left on both side portions ofthe gate electrodes 4 a, 4 b by etching back the insulating layer.

[0078] Then, in the p-type well 1 a, the n-type impurity ision-implanted once again into the first to third n-type impuritydiffusion regions 5 a to 5 c by using the gate electrodes 4 a, 4 b andthe sidewall spacers 6 as a mask. Thus, high-concentration impurityregions are formed in the first to third n-type impurity diffusionregions 5 a to 5 c respectively.

[0079] In this case, in one p-type well 1 a, the first n-type impuritydiffusion region 5 a formed between two gate electrodes 4 a, 4 b isconnected electrically to the bit line to be described later, and alsothe second and third n-type impurity diffusion regions 5 b, 5 c formednear both end sides of the p-type well 1 a are connected electrically tothe capacitor lower electrodes to be described later.

[0080] According to the above steps, two n-type MOS transistors T₁, T₂having the gate electrodes 4 a, 4 b and the n-type impurity diffusionregions 5 a to 5 c of the LDD structure are formed in the p-type well 1a while using one n-type impurity diffusion region 5 a commonly.

[0081] Then, as a cover layer 7 for covering the MOS transistors T₁, T₂,a silicon oxide nitride (SiON) layer of about 200 nm thickness is formedon the overall surface of the silicon substrate 1 by the plasma CVDmethod. Then, a silicon oxide (SiO₂) layer of about 1.0 μm thickness isformed as a first interlayer insulating layer 8 on the cover layer 7 bythe plasma CVD method using the TEOS gas.

[0082] Then, the first interlayer insulating layer 8 is annealed at thetemperature of 700° C. for 30 minute in the nitrogen atmosphere at theatmospheric pressure, for example, whereby the first interlayerinsulating layer 8 is densified. Then, an upper surface of the firstinterlayer insulating layer 8 is planarized by the CMP (ChemicalMechanical Polishing) method.

[0083] Then, as shown in FIG. 2B, the first interlayer insulating layer8 and the cover layer 7 are etched by using a resist pattern (notshown). Thus, first, second, and third contact holes 8 a, 8 b, 8 c areformed on the first, second, and third n-type impurity diffusion regions5 a, 5 b, 5 c in the memory cell region respectively.

[0084] Next, steps required until a structure shown in FIG. 2C is formedwill be explained hereunder.

[0085] First, a titanium (Ti) layer of 20 nm thickness and a titaniumnitride (TiN) layer of 50 nm thickness are formed sequentially as a gluelayer 9 a on the first interlayer insulating layer 8 and in the first tothird contact holes 8 a to 8 c by the sputter method. Then, a tungsten(W) layer 9 b is grown on the glue layer 9 a by the CVD method using WF₆to fill perfectly insides of the contact holes 8 a to 8 c.

[0086] Then, the tungsten layer 9 b and the glue layer 9 a are polishedby the CMP method to remove from an upper surface of the firstinterlayer insulating layer 8. As a result, the tungsten layer 9 b andthe glue layer 9 a being left in the first, second, and third contactholes 8 a, 8 b, 8 c respectively are used as first, second, and thirdconductive plugs 10 a, 10 b, 10 c. The first, second, and thirdconductive plugs 10 a, 10 b, 10 c are connected to the first, second,and third n-type impurity diffusion regions 5 a, 5 b, 5 c respectively.Also, the first conductive plug 10 a is connected electrically to thebit line to be described later, and the second and third conductiveplugs 10 b, 10 c are connected electrically to the capacitors to bedescribed later respectively.

[0087] Then, the first interlayer insulating layer 8 is exposed to thenitrogen plasma at the substrate temperature of 350° C. for 120 second.

[0088] Then, as shown in FIG. 2D, an iridium layer is formed as aconductive oxygen-barrier metal layer 11 on the first to thirdconductive plugs 10 a to 10 c and the first interlayer insulating layer8 by the sputter. The iridium layer is formed to have a thickness enoughto prevent the abnormal oxidation of the second and third conductiveplugs 10 b, 10 c. In order to prevent the abnormal oxidation of theconductive plugs 10 a to 10 c caused when the annealing is carried outat the substrate temperature of 550° C. in the oxygen-containingatmosphere, the iridium layer is formed to have the thickness of 200 nm,for example, and is also formed to increase such thickness by 100 nmevery time when the, substrate temperature is increased by 100° C.

[0089] Then, resist patterns are formed as a mask M₁ on theoxygen-barrier metal layer 11 over the second and third conductive plugs10 b, 10 c and their peripheral regions.

[0090] Then, as shown in FIG. 2E, the oxygen-barrier metal layer 11 inthe region that is not covered with the mask M₁ is etched, and thus theoxygen-barrier metal layers 11 are left like an island on the second andthird conductive plugs 10 b, 10 c and their peripheral regions.Accordingly, the first conductive plug 10 a is exposed. Then, the masksM₁ are removed. In this case, a hard mask made of titanium nitride,silicon oxide, or the like may be employed as the mask M₁. The hard maskconsists of inorganic material, unlike the resist mask made of organicmaterial.

[0091] Then, as shown in FIG. 2F, a silicon oxide nitride (SiON) layeror a silicon nitride (Si₃N₄) layer is formed as an oxidation-preventinginsulating layer 12 on the first conductive plug 10 a, theoxygen-barrier metal layers 11, and the first interlayer insulatinglayer 8 by the CVD method to have a thickness of 100 nm, for example.The SiON layer or the Si₃N₄ layer of 100 nm thickness has such acapability that is able to prevent the oxidation of the first conductiveplug 10 a in the oxygen annealing at about 650° C.

[0092] Then, an insulating adhesion layer 13 is formed on theoxidation-preventing insulating layer 12. The insulating adhesion layer13 is formed to improve the adhesion to the capacitor lower electrode tobe described later. As the insulating adhesion layer 13, a silicon oxide(SiO₂) layer of 100 nm thickness is formed by the CVD method using TEOS,for example.

[0093] Then, as shown in FIG. 2G, while making the oxygen-barrier metallayers 11 function as a stopper layer, the insulating adhesion layer 13and the oxidation-preventing insulating layer 12 are polished by the CMPmethod to expose an upper surface of the oxygen-barrier metal layers 11.In this case, polished surfaces of the oxygen-barrier metal layers 11,the insulating adhesion layer 13, and the oxidation-preventinginsulating layer 12 are made flat.

[0094] Then, as shown in FIG. 2H, a first conductive layer 14 is formedon the oxygen-barrier metal layers 11, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13. As the firstconductive layer 14, an iridium (Ir) layer 14 w of 200 nm thickness, aniridium oxide (IrO₂) layer 14 x of 30 nm thickness, a platinum oxide(PtO) layer 14 y of 30 nm thickness, and a platinum (Pt) layer 14 z of50 nm thickness, for example, are formed in sequence by the sputter.

[0095] In this case, the insulating adhesion layer 13 is annealed toprevent the peeling-off of the layer, for example, before or after thefirst conductive layer 14 is formed. As the annealing method, RTA (RapidThermal Annealing) executed at 750° C. for 60 second in the argonatmosphere, for example, may be employed.

[0096] Then, a PZT layer of 200 nm thickness, for example, is formed asa ferroelectric layer 15 on the first conductive layer 14 by the sputtermethod. As the method of forming the ferroelectric layer 15, there arethe MOD (Metal Organic Desposition) method, the MOCVD (Metal OrganicCVD) method, the sol-gel method, etc. in addition to this. Also, as thematerial of the ferroelectric layer 15, other PZT material such asPLCSZT, PLZT, etc., the Bi-layered structure compound material such asSrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and other metal oxide ferroelectricsubstance may be employed in addition to PZT.

[0097] Then, the ferroelectric layer 15 is annealed in theoxygen-containing atmosphere to crystallize. As such annealing, two-stepRTA process having the first step that is executed at the substratetemperature of 600° C. for 90 second in the mixed-gas atmospherecontaining argon (Ar) and oxygen (O₂) and the second step that isexecuted at the substrate temperature of 750° C. for 60 second in theoxygen atmosphere, for example, is employed.

[0098] An iridium oxide (IrO₂) of 200 nm thickness, for example, isformed as a second conductive layer 16 on the ferroelectric layer 15 bythe sputter method.

[0099] Then, a TiN layer and a SiO₂ layer are formed in sequence as ahard mask 17 on the second conductive layer 16. The TiN layer is formedby the sputter, and the SiO₂ layer is formed by the CVD method usingTEOS. The hard masks 17 are patterned into the capacitor planar shapeover the oxygen-barrier metal layers 11 and their peripheries by thephotolithography method.

[0100] Then, the second conductive layer 16, the ferroelectric layer 15,and the first conductive layer 14 in the region that is not covered withthe hard masks 17 are etched sequentially. Thus, the capacitors Q areformed on the oxygen-barrier metal layers 11, the insulating adhesionlayer 13, and the oxidation-preventing insulating layer 12. In thiscase, the second conductive layer 16, the ferroelectric layer 15, andthe first conductive layer 14 are etched by the sputter reaction in theatmosphere containing a halogen element.

[0101] As shown in FIG. 2I, each of the capacitors Q consists of a lowerelectrode 14 a made of the first conductive layer 14, a dielectric layer15 a made of the ferroelectric layer 15, and an upper electrode 16 amade of the second conductive layer 16.

[0102] Two capacitors Q are formed over one well 1 a. The lowerelectrodes 14 a of the capacitors Q are connected electrically to thesecond or third n-type impurity diffusion region 5 b, 5 c via the secondor third conductive plug 10 b, 10 c respectively.

[0103] In this case, if the insulating adhesion layer 13 is etched informing the capacitors Q, the underlying oxidation-preventing insulatinglayer 12 functions as the etching stopper, and thus the first conductiveplug 10 a is never exposed.

[0104] The hard masks 17 are removed after patterns of the capacitors Qare formed.

[0105] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minute in the furnace containingthe oxygen, for example.

[0106] In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11 and also the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

[0107] Although the above-mentioned thermal processes are required toform the capacitors Q, the first conductive plug 10 a made of tungstenis not abnormally oxidized in the condition of which the thickness ofthe silicon nitride layer used as the insulating adhesion layer 13 isset to 70 nm.

[0108] Also, assume that the iridium layer of 200 nm thickness ispresent on the second and third conductive plugs 10 b, 10 c made oftungsten, the second and third conductive plugs 10 b, 10 c areabnormally oxidized by the above oxygen annealing to cause the contactfailure. Experimentally the thickness of the Ir layer as theoxygen-barrier metal layer 11 must be further increased by 100 nm toincrease the annealing temperature by 100° C. For example, in order toform the tungsten plug, which can stand the thermal process, directlyunder the lower electrodes 14 a, the oxygen-barrier metal layer made ofIr having a thickness of more than 400 nm must be formed. In thisembodiment, a total thickness of the Ir layer, which consists of theiridium layer constituting the oxygen-barrier metal layers 11 and theiridium layer 14 z constituting the first conductive layer 14, is set to400 nm. Thus, the abnormal oxidation of the second and third conductiveplugs 10 b, 10 c are prevented.

[0109] Then, as shown in FIG. 2J, alumina of 50 nm thickness is formedas a capacitor protection layer 18 on the capacitors Q and theinsulating adhesion layer 13 by the sputter. This capacitor protectionlayer 18 protects the capacitors Q from the process damage, and may beformed of PZT in addition to alumina. Then, the capacitors Q areannealed at 650° C. for 60 minute in the oxygen atmosphere in thefurnace.

[0110] Then, a silicon oxide (SiO₂) of about 1.0 μm thickness is formedas a second interlayer insulating layer 19 on the capacitor protectionlayer 18 by the plasma CVD method using the HDP (High Density Plasma)equipment.

[0111] Then, an upper surface of the second interlayer insulating layer19 is planarized by the CMP method. In this example, a remainingthickness of the second interlayer insulating layer 19 after CMP is setto almost 300 nm on the upper electrodes 16 a.

[0112] Then, as shown in FIG. 2K, the second interlayer insulating layer19, the capacitor protection layer 18, the insulating adhesion layer 13,and the oxidation-preventing insulating layer 12 are etched by using aresist mask (not shown). Thus, a fourth contact hole 19 a is formed onthe first conductive plug 10 a.

[0113] Then, as shown in FIG. 2L, a TiN layer of 50 nm thickness isformed as a glue layer 20 a in the fourth contact hole 19 a and on thesecond interlayer insulating layer 19 by the sputter method. Then, atungsten layer 20 b is grown on the glue layer 20 a by the CVD method tobury perfectly the inside of the fourth contact hole 19 a.

[0114] Then, as shown in FIG. 2M, the tungsten layer 20 b and the gluelayer 20 a are polished by the CMP method to remove from an uppersurface of the second interlayer insulating layer 19. Then, the tungstenlayer 20 b and the glue layer 20 a left in the fourth contact hole 19 aare used as a fourth conductive plug 21.

[0115] Accordingly, the fourth conductive plug 21 is connected to thefirst conductive plug 10 a to form the via-to-via contact, and isconnected electrically to the first impurity diffusion region 5 a.

[0116] Then, the second interlayer insulating layer 19 is annealed at350° C. for 120 second in the nitrogen plasma atmosphere.

[0117] Then, as shown in FIG. 2N, a SiO₂ layer of 100 nm thickness isformed as a second oxidation-preventing insulating layer 22 on thefourth conductive plug 21 and the second interlayer insulating layer 19by the CVD method.

[0118] Then, holes 23 are formed on the upper electrodes 16 a of thecapacitors Q by patterning the second oxidation-preventing insulatinglayer 22, the second interlayer insulating layer 19, and the capacitorprotection layer 18 by means of the photolithography method. Thecapacitors Q that are subjected to the damage by forming the holes 23are recovered by the annealing. Such annealing is carried out at thesubstrate temperature of 550° C. for 60 minute in the oxygen-containingatmosphere, for example.

[0119] Next, steps required until a structure shown in FIG. 2O is formedwill be explained hereunder.

[0120] First, the second oxidation-preventing insulating layer 22 formedon the second interlayer insulating layer 19 is removed by theetching-back. Thus, a surface of the fourth conductive plug 21 isexposed.

[0121] Then, a multi-layered metal layer is formed in the holes 23 onthe upper electrodes 16 a of the capacitors Q and on the secondinterlayer insulating layer 19. As the multi-layered metal layer, a Tilayer of 60 nm thickness, a TiN layer of 30 nm thickness, an Al—Cu layerof 400 nm thickness, a Ti layer of 5 nm thickness, and a TiN layer of 70nm thickness are formed sequentially.

[0122] Then, a conductive pad 24 a, which is connected to the fourthconductive plug 21, and first-layer metal wirings 24 b, 24 c, which areconnected to the upper electrodes 16 a via the holes 23, are formed bypatterning the multi-layered metal layer.

[0123] In this case, in order to prevent the reduction of the patternprecision by the reflection of the exposure light upon patterning of themulti-layered metal layer, the method of forming a reflection preventinglayer (not shown) made of silicon oxide nitride (SiON), or the like onthe multi-layered metal layer to have a thickness of 30 nm, then formingresist patterns such as wiring shapes, etc. by coating a resist on thereflection preventing layer and exposing/developing the resist, and thenetching the multi-layered metal layer by using the resist patterns isemployed. The reflection preventing layer may be left as it is after thepatterning of the multi-layered metal layer.

[0124] Then, a third interlayer insulating layer 25 is formed on thesecond interlayer insulating layer 19, the first-layer metal wirings 24b, 24 c, and the conductive pad 24 a.

[0125] Then, a bit-line contact hole 25 a is formed on the conductivepad 24 a by patterning the third interlayer insulating layer 25. Also, afifth conductive plug 26 made of a TiN layer and a W layer sequentiallyfrom the bottom is formed in the hole 25 a.

[0126] Then, a second-layer metal wiring containing a bit line 27 isformed on the third interlayer insulating layer 25. The bit line 27 hasthe multi-layered metal structure, like the first-layer metal wirings 24b, 24 c. Also, when the bit line 27 is connected to the fifth conductiveplug 26, such bit line 27 is connected electrically to the first n-typeimpurity diffusion region 5 a via the conductive pad 24 a, the fourthconductive plug 21, and the first conductive plug 10 a.

[0127] Then, an insulating layer for covering the second-layer metalwiring, etc. are formed, and finally a cover layer made of a TEOSmaterial silicon oxide layer and a silicon nitride layer is formed. Buttheir details will be omitted herein.

[0128] In the above embodiment, under the lower electrodes 14 aconstituting the capacitors Q, the second and third conductive plugs 10b, 10 c are covered with the oxygen-barrier metal layer 11 and also thefirst conductive plug 10 a and the first interlayer insulating layer 8,which are connected to the bit line 27, are covered with theoxidation-preventing insulating layer 12. Hence, in the crystallizationannealing and the recovery annealing of the ferroelectric layer 15, theabnormal oxidation of the first conductive plug 10 a is prevented by theoxidation-preventing insulating layer 12 and also the abnormal oxidationof the second and third conductive plugs 10 b, 10 c are prevented by theoxygen-barrier metal layer 11. Also, since the oxidation-preventinginsulating layer 12 still covers the first conductive plug 10 a untilthe fourth contact hole 19 a is formed, the first conductive plug 10 ais never oxidized by the annealing applied in the formation of thecapacitors Q and later steps. In addition, in the case that the secondinterlayer insulating layer 19 is formed over the first conductive plug10 a, the first conductive plug 10 a is prevented from being oxidizedsince the first conductive plug 10 a is covered with theoxidation-preventing insulating layer 12.

[0129] In addition, patterned side surfaces of the oxygen-barrier metallayer 11 are covered with the oxidation-preventing insulating layer 12.Therefore, if the size of the oxygen-barrier metal layer 11 is formedsubstantially identically to the second and third conductive plugs 10 b,10 c, the oxygen is prevented from entering into the oxygen-barriermetal layer 11 from the side and thus the abnormal oxidation of thesecond and third conductive plugs 10 b, 10 c is never caused.

[0130] The oxygen-barrier metal layer 11 formed on the second and thirdconductive plugs 10 b, 10 c respectively functions as a stopper when theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are polished by the CMP method. As a result, upper surfaces ofthe oxygen-barrier metal layer 11, the oxidation-preventing insulatinglayer 12, and the insulating adhesion layer 13 are made flat, and thusdegradation of the crystal of the ferroelectric layer 15 formed on thefirst conductive layer 14 is prevented.

[0131] Also, since the FeRAM has level difference on the firstinterlayer insulating layer 8 by the ferroelectric capacitor rather thanthe normal logic product, it is possible that an aspect ratio of thecontact hole from the first-layer metal wiring 24 b to the first n-typeimpurity diffusion region 5 a is increased. If it is tried to form thiscontact hole by the etching at one step like the prior art shown inFIGS. 1A to 1C, not only the etching itself becomes difficult but alsothe filling of the glue layer into the contact hole becomes severe. Theup-to-date equipment is needed to eliminate such problem.

[0132] In contrast, like the present embodiment, the via-to-via contactis formed between the first n-type impurity diffusion region 5 a and thecontact pad 24 a via two conductive plugs 21, 10 a. As a result, notonly yield of the FeRAM product can be increased but also the existingequipment can be still employed, so that there can be achieved such anadvantage that reduction in the development cost and the step cost canbe implemented.

[0133] (Second Embodiment)

[0134] In the first embodiment, the iridium layer formed on the secondand third conductive plugs 10 b, 10 c as the oxygen-barrier metal layer11 and the iridium layer 14 w formed as the lowermost layer portion ofthe lower electrode 14 a of the capacitor Q are formed by separatesteps.

[0135] Therefore, in the present embodiment, a structure in which one oftwo iridium layers is omitted will be explained hereunder.

[0136]FIGS. 3A to 3I are sectional views showing steps of manufacturinga semiconductor device according to a second embodiment of the presentinvention.

[0137] First, as shown in FIG. 3A, in compliance with the steps shown inthe first embodiment, the MOS transistors T₁, T₂ are formed on thesilicon substrate 1 and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed.

[0138] Then, as shown in FIG. 3B, the iridium layer is formed as aconductive oxygen-barrier metal layer 11 a on the first to thirdconductive plugs 10 a to 10 c and the first interlayer insulating layer8 by the sputter. The oxygen-barrier metal layer 11 a constitutes a partof the lower electrode of the capacitor Q, as described later.

[0139] The iridium layer acting as the oxygen-barrier metal layer 11 ais formed to have a thickness enough to prevent the abnormal oxidationof the first to third conductive plugs 10 a to 10 c. For instance, inorder to prevent the abnormal oxidation of the first to third conductiveplugs 10 a to 10 c in the annealing at the substrate temperature of 550°C. in the oxygen-containing atmosphere, such iridium layer is formed tohave a thickness of 200 nm, for example, and also is formed to add thethickness by 100 nm every time when the substrate temperature isincreased by 100° C. In other words, when the iridium layer has thethickness of 400 nm, the iridium layer can prevent the oxidation of thefirst to third conductive plugs 10 a to 10 c from the oxygen annealingat 750° C.

[0140] Then, masks M₂ are formed on the oxygen-barrier metal layer 11 aover the second and third conductive plugs 10 b, 10 c and theirperipheral areas. A planar shape of the mask M₂ is set equal to theshape of the lower electrode of the capacitor. As the mask M₂, a hardmask made of titanium nitride, silicon oxide, or the like may beemployed.

[0141] Then, as shown in FIG. 3C, the oxygen-barrier metal layer 11 a inthe region that is not covered with the masks M₂ is etched. Thus, theoxygen-barrier metal layer 11 a is left on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas to have a size ofthe capacitor. As the etching gas of the oxygen-barrier metal layer 11a, a halogen gas is used. Now, the first conductive plug 10 a isexposed.

[0142] Then, the masks M₂ are removed.

[0143] Then, as shown in FIG. 3D, the silicon oxide nitride (SiON) layeror the silicon nitride (Si₃N₄) layer of 100 nm thickness, for example,is formed as the oxidation-preventing insulating layer 12 on the firstconductive plug 10 a, the oxygen-barrier metal layer 11 a, and the firstinterlayer insulating layer 8 by the CVD method. Then, the silicon oxide(SiO₂) layer of 300 nm thickness, for example, is formed as theinsulating adhesion layer 13 on the oxidation-preventing insulatinglayer 12 by the CVD method using TEOS, for example.

[0144] Then, as shown in FIG. 3E, an upper surface of the oxygen-barriermetal layer 11 a is exposed by polishing the insulating adhesion layer13 and the oxidation-preventing insulating layer 12 by means of the CMPmethod while causing the oxygen-barrier metal layer 11 a to function asthe stopper layer. In this case, upper surfaces of the oxygen-barriermetal layer 11 a, the insulating adhesion layer 13, and theoxidation-preventing insulating layer 12 are made flat by the CMPmethod.

[0145] Then, as shown in FIG. 3F, a IrO₂ layer 14 x of 30 nm thickness,a PtO layer 14 y of 30 nm thickness, and a Pt layer 14 z of 50 nmthickness, for example, are formed in sequence as a first conductivelayer 14 b on the oxygen-barrier metal layer 11 a, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 by the sputter.

[0146] In this case, the insulating adhesion layer 13 is annealed toprevent the peeling-off of the layer, for example, before or after thefirst conductive layer 14 b is formed. As the annealing method, RTA(Rapid Thermal Annealing) executed at 750° C. for 60 second in the argonatmosphere, for example, may be employed.

[0147] Then, the PZT layer of 200 nm thickness, for example, is formedas the ferroelectric layer 15 on the first conductive layer 14 b by thesputter method. As the method of forming the ferroelectric layer 15,there are the MOD method, the MOCVD method, the sol-gel method, etc. inaddition to this. Also, as the material of the ferroelectric layer 15,other PZT material such as PLCSZT, PLZT, etc., the Bi-layered structurecompound material such as SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and othermetal oxide ferroelectric substance may be employed in addition to PZT.

[0148] Then, the ferroelectric layer 15 is annealed in theoxygen-containing atmosphere to crystallize. As such annealing, two-stepRTA process having the first step that is executed at the substratetemperature of 600° C. for 90 second in the mixed-gas atmosphereconsisting of Ar and O₂ and the second step that is executed at thesubstrate temperature of 750° C. for 60 second in the oxygen atmosphere,for example, is employed.

[0149] Then, the IrO₂ layer of 200 nm thickness, for example, is formedas the second conductive layer 16 on the ferroelectric layer 15 by thesputter method.

[0150] Then, the TiN layer and the SiO₂ layer are formed in sequence asthe hard mask 17 on the second conductive layer 16. The TiN layer isformed by the sputter, and the SiO₂ layer is formed by the CVD methodusing TEOS. The hard masks 17 are patterned into the planar shape, whichis almost same as the oxygen-barrier metal layers 11 a, over the secondand third conductive plugs 10 b, 10 c.

[0151] Then, the second conductive layer 16, the ferroelectric layer 15,and the first conductive layer 14 b in the region that is not coveredwith the hard masks 17 are etched sequentially. In this case, the secondconductive layer 16, the ferroelectric layer 15, and the firstconductive layer 14 b are etched by the sputter reaction in theatmosphere containing the halogen element. Here, since theoxidation-preventing insulating layer 12 functions as the etchingstopper even after the insulating adhesion layer 13 is etched by suchetching, the first conductive plug is never exposed.

[0152] According to the above, as shown in FIG. 3G, the capacitors Q areformed on the first interlayer insulating layer 8. The lower electrode14 a of the capacitor Q is made of the first conductive layer 14 b andthe oxygen-barrier metal layers 11 a. Also, the dielectric layer 15 a ofthe capacitor Q is made of the ferroelectric layer 15. Also, the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

[0153] Two capacitors Q are arranged over one well 1 a. These lowerelectrodes 14 a are connected electrically to the second or third n-typeimpurity diffusion region 5 b, 5 c via the second or third conductiveplug 10 b, 10 c respectively.

[0154] In this case, since a layer thickness of the first conductivelayer 14 b to be etched is thin rather than the first conductive layer14 in the first embodiment, the hard masks 17 can be formed thinner thanthe first embodiment.

[0155] The hard masks 17 are removed after patterns of the capacitors Qare formed.

[0156] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minute in the furnace containingthe oxygen, for example.

[0157] In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11 a, and also the oxidation resistance ofthe first conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

[0158] Although the above thermal processes are required to form thecapacitors Q, the first conductive plug 10 a made of tungsten is notabnormally oxidized by condition of which the thickness of the siliconnitride layer used as the insulating adhesion layer 13 is set to 70 nm.

[0159] Also, in the condition of the iridium layer of 400 nm thicknessformed on the second and third conductive plugs 10 b, 10 c made oftungsten, the abnormal oxidation of the second and third conductiveplugs 10 b, 10 c is not caused by the oxygen annealing.

[0160] Then, as shown in FIG. 3H, the alumina of 50 nm thickness isformed as the capacitor protection layer 18 on the capacitors Q, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 by the sputter. This capacitor protection layer 18 protects thecapacitors Q from the process damage, and may be formed of PZT inaddition to the alumina. Then, the capacitors Q are annealed at 650° C.for 60 minute in the oxygen atmosphere in the furnace.

[0161] Then, as shown in FIG. 3I, in compliance with the steps shown inthe first embodiment, the fourth conductive plug 21, the conductive pad24 a, the first-layer metal wirings 24 b, 24 c, the third interlayerinsulating layer 25, the fifth conductive plug 26, the bit line 27, etc.are formed.

[0162] As described above, in the present embodiment, the oxygen-barriermetal layer 11 a constituting the lowermost layer of the lowerelectrodes 14 a of the capacitors Q is formed previously over the secondand third conductive plugs 10 b, 10 c to have the lower electrode shape,then the oxidation-preventing insulating layer 12 and the insulatingadhesion layer 13 are formed, then the oxygen-barrier metal layer 11 ais exposed by polishing the oxidation-preventing insulating layer 12 andthe insulating adhesion layer 13 by virtue of the CMP method, and thenremaining metal layers of the lower electrodes 14 a are formed on theoxygen-barrier metal layers 11 a. Here, the iridium layer, for example,is formed as the oxygen-barrier metal and lower electrode.

[0163] In the first embodiment, the iridium layers constituting theoxygen-barrier metal layer and the lower electrode respectively areformed by separate steps and patterned separately. In the presentembodiment, the iridium layer is formed by one layer forming step andone patterning step, and therefore there is such a merit that a part ofsteps of forming the lower electrodes can be reduced.

[0164] By the way, like the first embodiment, in the crystallizationannealing of the ferroelectric layer 15 and the recovery annealing afterthe formation of the capacitors Q, the abnormal oxidation of the secondand third conductive plugs 10 b, 10 c is prevented by the oxygen-barriermetal layers 11 a and also the abnormal oxidation of the firstconductive plug 10 a is prevented by the oxidation-preventing insulatinglayer 12.

[0165] In addition, since upper surfaces of the oxygen-barrier metallayers 11 a, the oxidation-preventing insulating layer 12, and theinsulating adhesion layer 13 are planarized by the CMP method, the firstconductive layer 14 b formed on the oxygen-barrier metal layers 11 a,the oxidation-preventing insulating layer 12, and the insulatingadhesion layer 13 becomes flat in the neighborhood of the oxygen-barriermetal layers 11 a. Thus, degradation of the crystal of the ferroelectriclayer 15 formed on the first conductive layer 14 b is prevented.

[0166] Also, the conductive plugs 10 a, 21 for the bit-line contact areformed separately in the first interlayer insulating layer 8 and thesecond interlayer insulating layer 19. As a result, not only the yieldof the FeRAM product can be increased but also the existing equipmentcan be still employed, so that there can be achieved such an advantagethat reduction in the development cost and the step cost can beimplemented.

[0167] In this case, if the oxidation-preventing insulating layer 12 isformed thicker than the oxygen-barrier metal layers 11 a, the insulatingadhesion layer 13 may be omitted.

[0168] (Third Embodiment)

[0169] In the lower electrodes 14 a of the capacitors Q formed inaccordance with the steps shown in the second embodiment, thepeeling-off of the IrO layer 14 x from the oxygen-barrier metal layer 11a rarely occurs.

[0170] Therefore, a structure for preventing the peeling-off of the IrOlayer 14 x from the oxygen-barrier metal layer 11 a without fail in themulti-layered structure, which constitutes the lower electrodes 14 a ofthe capacitors Q, and a method of forming the same will be explainedhereunder.

[0171]FIGS. 4A to 4E are sectional views showing steps of manufacturinga semiconductor device according to a third embodiment of the presentinvention.

[0172] First, as shown in FIG. 4A, in compliance with the steps shown inthe first embodiment, the MOS transistors T₁, T₂ are formed on thesilicon substrate 1 and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed. Then, in compliance with the steps shown in the secondembodiment, the oxygen-barrier metal layers 11 a each having the samesize as the lower electrode of the capacitor Q are formed on the firstto third conductive plugs 10 a to 10 c and their peripheral areas. Theoxygen-barrier metal layer 11 a is the iridium layer having a thicknessof 400 nm, for example. Then, the oxidation-preventing insulating layer12 and the insulating adhesion layer 13 are formed in sequence on thefirst conductive plug 10 a, the oxygen-barrier metal layers 11 a, andthe first interlayer insulating layer 8. Then, the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13 are polished bythe CMP method to expose the upper surface of the oxygen-barrier metallayers 11 a.

[0173] Then, as shown in FIG. 4B, a conductive adhesion layer 35 isformed on the oxygen-barrier metal layers 11 a, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13. As theconductive adhesion layer 35, an iridium layer of 10 to 50 nm thickness,for example 30 nm, is formed by the sputter.

[0174] In this case, the insulating adhesion layer 13 is annealed toprevent the peeling-off of the layer, for example, before or after theconductive adhesion layer 35 is formed. As the annealing method, the RTAexecuted at 750° C. for 60 second in the argon atmosphere, for example,may be employed.

[0175] Then, as shown in FIG. 4C, the IrO₂ layer 14 x of 30 nmthickness, the PtO layer 14 y of 30 nm thickness, and the Pt layer 14 zof 50 nm thickness, for example, are formed in sequence as the firstconductive layer 14 b on the conductive adhesion layer 35 by thesputter.

[0176] Then, the PZT layer of 180 nm thickness, for example, is formedas the ferroelectric layer 15 on the first conductive layer 14 b by thesputter method or other method. Then, the ferroelectric layer 15 isannealed in the oxygen-containing atmosphere under the same conditionsas the second embodiment to crystallize. Then, the IrO₂ of 200 nmthickness, for example, is formed as the second conductive layer 16 onthe ferroelectric layer 15 by the sputter method.

[0177] Then, the hard masks 17 are formed on the second conductive layer16 under the same conditions as the second embodiment.

[0178] Then, the second conductive layer 16, the ferroelectric layer 15,the first conductive layer 14 b, and the conductive adhesion layer 35 inthe region that is not covered with the hard masks 17 are etchedsequentially. In this case, respective layers from the first conductivelayer 14 b to the conductive adhesion layer 35 are etched by the sputterreaction in the atmosphere containing the halogen element. Therefore,since the oxidation-preventing insulating layer 12 functions as theetching stopper even after the insulating adhesion layer 13 is etched bysuch etching, the first conductive plug is never exposed.

[0179] The hard masks 17 are removed after the patterns of thecapacitors Q are formed.

[0180] With the above, as shown in FIG. 4D, the capacitors Q are formedon the first interlayer insulating layer 8. The lower electrode 14 a ofthe capacitor Q is made of the first conductive layer 14 b, theconductive adhesion layer 35, and the oxygen-barrier metal layers 11 a.Also, the dielectric layer 15 a of the capacitor Q is made of theferroelectric layer 15. Also, the upper electrode 16 a of the capacitorQ is made of the second conductive layer 16.

[0181] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing of the capacitors Q isexecuted. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minute in the furnace containingthe oxygen, for example.

[0182] Then, as shown in FIG. 4E, in compliance with the same steps asthe second embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 4E, the same referencesymbols as those in FIG. 3I denote the same elements.

[0183] In the present embodiment described above, the upper surface ofthe oxygen-barrier metal layers 11 a having the shape of the capacitorslower electrode is exposed by polishing the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13, then theconductive adhesion layer 35 is formed on the oxygen-barrier metallayers 11 a, the oxidation-preventing insulating layer 12, and theinsulating adhesion layer 13, and then the first conductive layer 14 b,the ferroelectric layer 15, and the second conductive layer 16 areformed sequentially on the conductive adhesion layer 35.

[0184] According to this, as shown in FIG. 4B, since the conductiveadhesion layer 35 is interposed between the polished surface of theoxygen-barrier metal layers 11 a and the first conductive layer 14 b,the IrO₂ layer 14 x constituting the first conductive layer 14 b isprevented from peeling off from the oxygen-barrier metal layers 11 a.Such prevention of the peeling-off has been checked based on theexperiment.

[0185] It may be considered that, when the oxidation-preventinginsulating layer 12 and the insulating adhesion layer 13 are polished,the surface of the oxygen-barrier metal layers 11 a is altered inquality. If the conductive adhesion layer 35 is not formed, theoxygen-barrier metal layers 11 a and the IrO₂ layer 14 x are put in thestate that they are easily peeled off because they are patterned intothe almost same planar shape respectively.

[0186] In contrast, in the state of which the conductive adhesion layer35 made of the same material as the oxygen-barrier metal layers 11 a isformed on the oxygen-barrier metal layers 11 a, such conductive adhesionlayer 35 is formed to have good adhesiveness to the oxygen-barrier metallayers 11 a and also the adhesiveness of the conductive adhesion layer35, whose surface is not altered in quality, to the IrO₂ layer 14 x isimproved.

[0187] Therefore, according to the present embodiment, if theoxygen-barrier metal layers 11 a is formed in the same size as the lowerelectrodes 14 a of the capacitor Q, the lower electrodes 14 a is neverlifted up because of the peeling-off.

[0188] In this case, in the above embodiment, the conductive adhesionlayer 35 is made of the same material as the oxygen-barrier metal layers11 a. But such conductive adhesion layer may be formed of otherconductive material that has good adhesiveness to the oxygen-barriermetal layers 11 a.

[0189] (Fourth Embodiment)

[0190] In the first and second embodiments, there is employed such astructure that the oxygen-barrier metal layers 11 or 11 a is formed onthe second or third conductive plug 10 b, 10 c formed directly under thecapacitors Q and the oxidation-preventing insulating layer 12 is formedon the first conductive plug 10 a.

[0191] In the present embodiment, to form the oxygen-barrier metal layeron not only the second and third conductive plugs 10 b, 10 c, which areformed directly under the capacitors Q, but also the first conductiveplug 10 a, which is not formed directly under the capacitors Q, will beexplained hereunder.

[0192]FIGS. 5A to 5G are sectional views showing steps of manufacturinga semiconductor device according to a fourth embodiment of the presentinvention.

[0193] First, steps required until a structure shown in FIG. 5A isformed will be explained hereunder.

[0194] Like the case shown in FIG. 3A, in compliance with the stepsshown in the second embodiment, the MOS transistors T₁, T₂ are formed onthe silicon substrate 1 and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed.

[0195] Then, as shown in FIG. 3B, the iridium layer of 400 nm thicknessis formed as the conductive oxygen-barrier metal layer 11 a on the firstto third conductive plugs 10 a to 10 c and the first interlayerinsulating layer 8 by the sputter. The oxygen-barrier metal layer 11 aconstitutes a part of the lower electrode of the capacitor Q, asdescribed later.

[0196] Then, the masks (not shown) are formed on the oxygen-barriermetal layer 11 a over the first, second and third conductive plugs 10 a,10 b, 10 c and their peripheral areas respectively. It is preferablethat, like the second embodiment, the hard mask should be employed asthe mask.

[0197] Then, the oxygen-barrier metal layer 11 a is left on the first,second, and third conductive plugs 10 a, 10 b, 10 c and their peripheralareas respectively by etching the region of the oxygen-barrier metallayer 11 a, which is not covered with the masks. Here, theoxygen-barrier metal layer 11 a left on the second and third conductiveplugs 10 b, 10 c is patterned into a size that is prevent the oxidationof the second and third conductive plugs 10 b, 10 c and act as the lowerelectrodes of the capacitors. Also, the oxygen-barrier metal layer 11 aleft on the first conductive plug 10 a is patterned into an island-likeshape that is prevent the oxidation of the first conductive plug 10 a.

[0198] Then, as shown in FIG. 5B, the silicon oxide (SiO₂) layer of 300nm thickness, for example, is formed as the insulating adhesion layer 13on the oxygen-barrier metal layer 11 a and the first interlayerinsulating layer 8 by the CVD method using TEOS, for example. In thiscase, like the second embodiment, the oxidation-preventing insulatinglayer 12 may be formed under the insulating adhesion layer 13.

[0199] Then, as shown in FIG. 5C, the upper surface of theoxygen-barrier metal layer 11 a is exposed by polishing the insulatingadhesion layer 13 by means of the CMP method while causing theisland-like oxygen-barrier metal layer 11 a to function as the stopperlayer. In this case, upper surfaces of the oxygen-barrier metal layer 11a and the insulating adhesion layer 13 are made flat by the CMP method.

[0200] Then, as shown in FIG. 5D, the IrO₂ layer 14 x of 30 nmthickness, the PtO layer 14 y of 30 nm thickness, and the Pt layer 14 zof 50 nm thickness, for example, are formed in sequence as the firstconductive layer 14 b on the oxygen-barrier metal layer 11 a and theinsulating adhesion layer 13 by the sputter.

[0201] In this case, the insulating adhesion layer 13 is annealed toprevent the peeling-off of the layer, for example, before or after thefirst conductive layer 14 b is formed. As the annealing method, the RTAexecuted at 750° C. for 60 second in the argon atmosphere, for example,may be employed.

[0202] Then, the PZT layer of 200 nm thickness, for example, is formedas the ferroelectric layer 15 on the first conductive layer 14 b by thesimilar method to that in the second embodiment. Then, the ferroelectriclayer 15 annealed in the oxygen-containing atmosphere to crystallize. Assuch annealing, two-step RTA process having the first step that isexecuted at the substrate temperature of 600° C. for 90 second in themixed-gas atmosphere consisting of Ar and O₂ and the second step that isexecuted at the substrate temperature of 750° C. for 60 second in theoxygen atmosphere, for example, is employed.

[0203] Then, the IrO₂ of 200 nm thickness, for example, is formed as thesecond conductive layer 16 on the ferroelectric layer 15 by the sputtermethod.

[0204] Then, the hard masks 17 having the same structure as the secondembodiment are formed on the second conductive layer 16. The hard masks17 are patterned into the planar shape, which is almost same as theoxygen-barrier metal layers 11 a, over the second and third conductiveplugs 10 b, 10 c by the photolithography method. The hard mask 17 has adouble-layered structure consisting of titanium nitride and siliconoxide, for example.

[0205] Then, like the second embodiment, the second conductive layer 16,the ferroelectric layer 15, and the first conductive layer 14 b in theregion that is not covered with the hard masks 17 are etchedsequentially. Then, the hard masks 17 are removed.

[0206] According to the above, as shown in FIG. 5E, the capacitors Q areformed on the first interlayer insulating layer 8. The lower electrode14 a of the capacitor Q is made of the first conductive layer 14 b andthe oxygen-barrier metal layers 11 a. Also, the dielectric layer 15 a ofthe capacitor Q is made of the ferroelectric layer 15. Also, the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

[0207] Two capacitors Q are arranged over one well 1 a. These lowerelectrodes 14 a are connected electrically to the second or third n-typeimpurity diffusion region 5 b, 5 c via the second or third conductiveplug 10 b, 10 c respectively.

[0208] In this case, since the layer thickness of the first conductivelayer 14 b to be etched is thin rather than the first conductive layer14 in the first embodiment, the hard masks 17 can also be formed thinnerthan the first embodiment.

[0209] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing is executed. Therecovery annealing in this case is carried out at the substratetemperature of 650° C. for 60 minute in the furnace containing theoxygen, for example.

[0210] In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a and the oxidation resistance of the first conductiveplug 10 a not positioned directly under the lower electrodes 14 a aredecided by the oxygen permeability of the oxygen-barrier metal layers 11a respectively.

[0211] Although the above thermal processes are required to form thecapacitors Q, the abnormal oxidization is not caused in the first tothird conductive plugs 10 a to 10 c by the oxygen annealing in thecondition of which the iridium layer of 400 nm, for example, is presentas the oxygen-barrier metal layers 11 a on the first to third conductiveplugs 10 a to 10 c, which are made of tungsten, and their peripheralareas respectively.

[0212] Then, as shown in FIG. 5F, the alumina of 50 nm thickness isformed as the capacitor protection layer 18 on the capacitors Q and theinsulating adhesion layer 13 by the sputter. This capacitor protectionlayer 18 protects the capacitors Q from the process damage, and may beformed of PZT in addition to the alumina. Then, the capacitors Q areannealed at 650° C. for 60 minute in the oxygen atmosphere in thefurnace.

[0213] Then, as shown in FIG. 5G, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed.

[0214] In this case, the fourth conductive plug 21 is formed in thesecond interlayer insulating layer 19 and the capacitor protection layer18 over the first n-type impurity diffusion region 5 a, and is connectedto the island-like oxygen-barrier metal layer 11 a. Hence, the bit line27 is connected electrically to the first n-type impurity diffusionregion 5 a via the fifth conductive plug 26, the conductive pad 24 a,the fourth conductive plug 21, the oxygen-barrier metal layer 11 a, andthe first conductive plug 10 a.

[0215] As described above, in the present embodiment, the island-likeoxygen-barrier metal layer 11 a is formed previously on the first tothird conductive plugs 10 a to 10 c, then the insulating adhesion layer13 is formed on oxygen-barrier metal layers 11 a and the firstinterlayer insulating layer 8, then the oxygen-barrier metal layer 11 ais exposed by polishing the insulating adhesion layer 13 by virtue ofthe CMP method, and then upper portions of the lower electrodes 14 a areformed on the oxygen-barrier metal layers 11 a that covers the secondand third conductive plugs 10 b, 10 c. Here, in the present embodiment,like the second embodiment, the iridium layer is also formed as theoxygen-barrier metal layer.

[0216] Accordingly, in the present embodiment, the oxygen-barrier metallayers 11 a is formed to use as not only the layer for preventing theabnormal oxidation of the second and third conductive plugs 10 b, 10 cbut also a part of the lower electrodes 14 a. Thus, such a merit isachieved that steps of forming the layers of the capacitors Q and stepsof patterning them are reduced rather than first embodiment.

[0217] In addition, since the oxygen-barrier metal layer 11 a is leftlike the island to cover the first conductive plug 10 a to which the bitline is connected electrically, steps of forming theoxidation-preventing insulating layer, shown in the first and secondembodiments, can be omitted.

[0218] As a result, in the crystallization annealing of theferroelectric layer 15 and in the recovery annealing after thecapacitors Q are formed, the abnormal oxidation of the first to thirdconductive plugs 10 a to 10 c is prevented by the oxygen-barrier metallayer 11 a.

[0219] In addition, since the upper surfaces of the oxygen-barrier metallayers 11 a and the insulating adhesion layer 13 are planarized by theCMP method, the first conductive layer 14 a formed on the oxygen-barriermetal layers 11 a and the insulating adhesion layer 13 is made flat inthe neighborhood of the oxygen-barrier metal layers 11 a. Thus,degradation of the crystal of the ferroelectric layer 15 formed on thefirst conductive layer 14 a is prevented.

[0220] Also, the conductive plugs 10 a, 21 for the bit-line contact areformed separately in the first interlayer insulating layer 8 and thesecond interlayer insulating layer 19. As a result, not only the yieldof the FeRAM product can be increased but also the existing equipmentcan be still employed, so that there can be achieved such a merit thatreduction in the development cost and the step cost can be implemented.

[0221] Here, the oxygen-barrier metal layer 11 a constitutes the lowerelectrode 14 a of the capacitor Q. The oxygen-barrier metal layer 11 amay be formed like the island that is narrower than the lower electrode14 a of the capacitor Q, like the first embodiment. In this case, thefirst conductive layer 14 having the quadruple-layered structureemployed in the first embodiment may be formed on the oxygen-barriermetal layer 11 a and the insulating adhesion layer 13 over the secondand third conductive plugs 10 b, 10 c, and then the lower electrodes 14a may be formed by patterning the first conductive layer 14.

[0222] In this case, as shown in FIG. 6, like the third embodiment, byadopting the conductive adhesion layer 35 formed between theoxygen-barrier metal layer 11 a and the IrO₂ layer 14 x in the lowerelectrode 14 a of the capacitor Q, the peeling-off in the lowerelectrode 14 a is prevented. In this case, the conductive adhesion layer35 on the island-like oxygen-barrier metal layer 11 a that covers thefirst conductive plug 10 a is removed by the etching.

[0223] (Fifth Embodiment)

[0224] In the above embodiments, the glue layer 9 a and the tungstenlayer 9 b are removed from the upper surface of the first interlayerinsulating layer 8 by the CMP process at the time of forming the firstto third conductive plugs 10 a to 10 c. It is possible that the erosionand the recess are generated around the first to third contact holes 8 ato 8 c in the CMP process. Since the object of the CMP process in thiscase is the glue layer 9 a and the tungsten layer 9 b, upper surfaces ofthe first to third conductive plugs 10 a to 10 c are polishedexcessively due to generation of the erosion and the recess around thecontact holes 8 a to 8 c. Thus, it is possible that the concave portionsare formed in the first to third conductive plugs 10 a to 10 c and theirperipheral areas. There is such a possibility that concave portions arealso generated slightly on upper surfaces of the oxygen-barrier metallayers 11, 11 a that are formed on the second and third conductive plugs10 b, 10 c in the situation that such concave portions are formed

[0225] In the above embodiments, the oxygen-barrier metal layers 11, 11a are planarized by the steps of polishing the insulating adhesion layer13 by means of the CMP. But such planarization is still insufficient insome cases.

[0226] If the concave portions are present on the oxygen-barrier metallayers 11, 11 a, such concave portions affect the lower electrode 14 a,the ferroelectric layer 15 a, and the upper electrode 16 a todeteriorate and also it is a chance to make the polarizationcharacteristic of the capacitor worse.

[0227] Therefore, in the present embodiment, a structure of capable ofplanarizing the oxygen-barrier metal layer much more and a method offorming the same will be explained hereunder.

[0228]FIGS. 7A to 7I are sectional views showing steps of manufacturinga semiconductor device according to a fifth embodiment of the presentinvention.

[0229] First, as shown in FIG. 7A, in compliance with the steps shown inthe first embodiment, the MOS transistors T₁, T₂ are formed on thesilicon substrate 1 and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed.

[0230] Then, as shown in FIG. 7B, a conductive oxygen-barrier metallayer 31 is formed on the first to third conductive plugs 10 a to 10 cand the first interlayer insulating layer 8 by the sputter.

[0231] In the present embodiment, the oxygen-barrier metal layer 31 hasa double-layered structure consisting of a lower metal layer 31 a and anupper metal layer 31 b. The conductive material that can be easilyplanarized by the CMP is selected as the upper metal layer 31 b. Forinstance, the lower metal layer 31 a made of iridium (Ir) and the uppermetal layer 31 b made of iridium oxide (IrO₂) are formed as theoxygen-barrier metal layer 31. The iridium layer is formed in the argonatmosphere by the sputter using an iridium target. Also, the iridiumoxide layer is formed in the atmosphere containing argon and oxygen bythe sputter using the iridium target. Here, the argon gas and the oxygengas are introduced at a ration of 80 and 20 respectively.

[0232] The oxygen-barrier metal layer 31 is formed to have the thicknessenough to prevent the abnormal oxidation of the second and thirdconductive plugs 10 b, 10 c. In order to prevent the abnormal oxidationof the second and third conductive plugs 10 b, 10 c in the annealing atthe substrate temperature of 550° C. in the oxygen-containingatmosphere, the lower Ir layer 31 a is formed to have a thickness of 200nm and the upper IrO₂ layer 31 b is formed to have a thickness of 200nm, for example.

[0233] In this case, in the present embodiment, a concept of the“oxygen-barrier metal” contains metal oxide.

[0234] Then, as shown in FIG. 7C, the oxygen-barrier metal layer 31 isleft on the second and third conductive plugs 10 b, 10 c and theirperipheral areas by etching the oxygen-barrier metal layer 31 whileusing a mask (not shown). In this case, it is preferable to use the hardmask as the mask, but the resist mask may be employed.

[0235] Then, as shown in FIG. 7D, the SiON layer or the Si₃N₄ layer of100 nm thickness, for example, is formed as the oxidation-preventinginsulating layer 12 on the oxygen-barrier metal layer 31 and the firstinterlayer insulating layer 8 by the CVD method. Then, the SiO₂ layer of300 nm thickness, for example, is formed as the insulating adhesionlayer 13 on the oxidation-preventing insulating layer 12 by the CVDmethod using TEOS, for example.

[0236] Then, as shown in FIG. 7E, an upper surface of the upper layer 31b of the oxygen-barrier metal layer 31 is exposed by polishing theinsulating adhesion layer 13 and the oxidation-preventing insulatinglayer 12 by virtue of the CMP process. The upper layer 31 b is scrapedup to a thickness of about 100 nm by executing the CMP processcontinuously.

[0237] Hence, successive upper surfaces of the oxygen-barrier metallayer 31, the insulating adhesion layer 13, and the oxidation-preventinginsulating layer 12 are planarized by the CMP method. In this case, asthe CMP slurry for the silicon oxide, the silicon nitride, and thesilicon nitride oxide, the slurry prepared by adding the water to SS-25manufactured by CABOT Inc., for example, is employed. According to this,the IrO₂ layer constituting the upper layer 31 b is planarized moreeasily than the Ir layer, and is employed as the sacrifice layer.

[0238] Then, as shown in FIG. 7F, the Ir layer 14 w of 200 nm thickness,the IrO₂ layer 14 x of 30 nm thickness, the PtO layer 14 y of 30 nmthickness, and the Pt layer 14 z of 50 nm thickness, for example, areformed in sequence as the first conductive layer 14 on the upper layer31 b of the oxygen-barrier metal layer 31, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13 by thesputter.

[0239] In this case, the insulating adhesion layer 13 is annealed toprevent the peeling-off of the layer, for example, before or after thefirst conductive layer 14 is formed. As the annealing method, the RTAexecuted at 750° C. for 60 second in the argon atmosphere, for example,may be employed.

[0240] Then, the PZT layer of 200 nm thickness, for example, is formedas the ferroelectric layer 15 on the first conductive layer 14 by thesputter method. As the method of forming the ferroelectric layer 15,there are the MOD method, the MOCVD method, the sol-gel method, etc. inaddition to this. Also, as the material of the ferroelectric layer 15,other PZT material such as PLCSZT, PLZT, etc., the Bi-layered structurecompound material such as SrBi₂Ta₂O₉, SrBi₂(Ta,Nb)₂O₉, etc., and othermetal oxide ferroelectric substance may be employed in addition to PZT.

[0241] Then, the ferroelectric layer 15 is annealed in theoxygen-containing atmosphere to crystallize. As such annealing, two-stepRTA process having the first step that is executed at the substratetemperature of 600° C. for 90 second in the mixed-gas atmosphereconsisting of Ar and O₂ and the second step that is executed at thesubstrate temperature of 750° C. for 60 second in the oxygen atmosphere,for example, is employed.

[0242] Then, the IrO₂ of 200 nm thickness, for example, is formed as thesecond conductive layer 16 on the ferroelectric layer 15 by the sputtermethod.

[0243] Then, the TiN layer and the SiO₂ layer are formed in sequence asthe hard mask 17 on the second conductive layer 16. The TiN layer isformed by the sputter, and the SiO₂ layer is formed by the CVD methodusing TEOS. The hard masks 17 are patterned into the planar shape of thecapacitor over the second and third conductive plugs 10 b, 10 c by thephotography method.

[0244] Then, the second conductive layer 16, the ferroelectric layer 15,and the first conductive layer 14 in the region that is not covered withthe hard masks 17 are etched sequentially. In this case, theferroelectric layer 15 is etched by the sputter reaction in theatmosphere containing the halogen element. Here, since theoxidation-preventing insulating layer 12 functions as the etchingstopper even after the insulating adhesion layer 13 is etched by suchetching, the first conductive plug is never exposed.

[0245] According to the above, as shown in FIG. 7G, the capacitors Q areformed on the first interlayer insulating layer 8. The lower electrode14 a of the capacitor Q is made of the first conductive layer 14. Also,the dielectric layer 15 a of the capacitor Q is made of theferroelectric layer 15. Also, the upper electrode 16 a of the capacitorQ is made of the second conductive layer 16.

[0246] Two capacitors Q are arranged over one well 1 a. These lowerelectrodes 14 a are connected electrically to the second or third n-typeimpurity diffusion region 5 b, 5 c via the second or third conductiveplug 10 b, 10 c respectively.

[0247] The hard masks 17 are removed after the patterns of thecapacitors Q are formed.

[0248] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing of the capacitors Q iscarried out. The recovery annealing in this case is carried out at thesubstrate temperature of 650° C. for 60 minute in the furnace containingthe oxygen, for example.

[0249] In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 31, and also the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

[0250] Although the above thermal processes are required to form thecapacitors Q, the first conductive plug 10 a made of tungsten is notabnormally oxidized in the condition of which the thickness of thesilicon nitride layer used as the insulating adhesion layer 13 is set to70 nm.

[0251] Also, in the condition of which the iridium layer of 400 nmthickness is present on the second and third conductive plugs 10 b, 10 cmade of tungsten, the second and third conductive plugs 10 b, 10 c arenot abnormally oxidized by the oxygen annealing.

[0252] In the present embodiment, a total thickness of the iridium layeris 400 nm under the ferroelectric layer 15 and also the IrO₂ layer stillremains about 100 nm in thick. In this case, since both layers preventsthe permeation of oxygen, the abnormal oxidation of the conductive plugs10 b, 10 c is not caused.

[0253] Then, as shown in FIG. 7H, the alumina of 50 nm thickness isformed as the capacitor protection layer 18 on the capacitors Q, theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 by the sputter. This capacitor protection layer 18 protects thecapacitors Q from the process damage, and may be formed of PZT inaddition to the alumina. In turn, the capacitors Q are annealed at 650°C. for 60 minute in the oxygen atmosphere.

[0254] Then, as shown in FIG. 7I, in compliance with the steps shown inthe first embodiment, the fourth conductive plug 21, the conductive pad24 a, the first-layer metal wirings 24 b, 24 c, the third interlayerinsulating layer 25, the fifth conductive plug 26, the bit line 27, etc.are formed.

[0255] As described above, in the present embodiment, the oxygen-barriermetal layer 31 having the double-layered structure is left like theisland on the second and third conductive plugs 10 b, 10 c, then theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are formed on the oxygen-barrier metal layer 31 and the firstinterlayer insulating layer 8, then the upper surface of theoxygen-barrier metal layer 31 is exposed by polishing theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 by virtue of the CMP process, and then the upper layer 31 b ofthe oxygen-barrier metal layer 31 is reduced in thickness by executingfurther the CMP process.

[0256] Since the upper layer 31 b of the oxygen-barrier metal layer 31is planarized more easily by the CMP than the Ir layer, it can befacilitated to eliminate the recess on the upper surface of the upperlayer 31 b caused by the concave portion generated on the second andthird conductive plugs 10 b, 10 c and their peripheral areas.

[0257] Therefore, since layers of the first conductive layer 14 and theferroelectric layer 15 formed on the upper layer 31 b can be formedflat, deterioration of the layer quality of the ferroelectric layer 15resulted from unevenness can be prevented. As a result, thecharacteristics of the capacitors Q formed by patterning the firstconductive layer 14, the ferroelectric layer 15, and the secondconductive layer 16 can be improved.

[0258] Also, the second and third conductive plugs 10 b, 10 c below thelower electrodes 14 a constituting the capacitors Q are covered with theoxygen-barrier metal layer 31 and the first conductive plug 10 a,connected to the bit line 27, and the first interlayer insulating layer8 are covered with the oxidation-preventing insulating layer 12. Hence,in the crystallization annealing or the recovery annealing of theferroelectric layer 15, the abnormal oxidation of the first conductiveplug 10 a is prevented by the oxidation-preventing insulating layer 12and also the abnormal oxidation of the second and third conductive plugs10 b, 10 c is prevented by the oxygen-barrier metal layer 31. Inaddition, the oxidation-preventing insulating layer 12 still covers thefirst conductive plug 10 a until the fourth contact hole 19 a is formed,the first conductive plug 10 a is never oxidized by the annealingapplied in the formation of the capacitors Q and subsequent steps.

[0259] Further, patterned side surfaces of the oxygen-barrier metallayer 31 are covered with the oxidation-preventing insulating layer 12.Therefore, if a size of the oxygen-barrier metal layer 31 is formedalmost equal to the second and third conductive plugs 10 b, 10 c, theoxygen is prevented from entering into the oxygen-barrier metal layer 31from their side surfaces and thus the abnormal oxidation of the secondand third conductive plugs 10 b, 10 c is not generated.

[0260] Also, in the present embodiment, the via-to-via contact is formedbetween the first n-type impurity diffusion region 5 a and the contactpad 24 a via two conductive plugs 21, 10 a. As a result, not only theyield of the FeRAM product can be increased but also the existingequipment can be still employed, so that there can be achieved such anadvantage that reduction in the development cost and the step cost canbe implemented.

[0261] In this case, like the oxygen-barrier metal layer 14 a in thesecond and third embodiments, the oxygen-barrier metal layer 31 havingthe above structure may be shaped into the planar shape, which has thesame size as the lower electrode 14 a of the capacitor Q, so as toconstitute a part of the lower electrode. Also, like the oxygen-barriermetal layers 11 a in the fourth embodiment, the oxygen-barrier metallayer 31 having the above structure may be left like the island on thefirst conductive plug 10 a.

[0262] (Sixth Embodiment)

[0263] In the first to fifth embodiments, in order to prevent theoxidation of the second and third conductive plugs 10 b, 10 c, theiridium layer is formed as the oxygen-barrier metal layer 11 or 11 a onthe second and third conductive plugs 10 b, 10 c.

[0264] The iridium layer is formed on the first interlayer insulatinglayer 8, which is formed by using TEOS, around the second and thirdconductive plugs 10 b, 10 c.

[0265] By the way, a plurality of semiconductor devices are formed via ascribing region on one sheet of silicon wafer. A plurality of alignmentmarks 40 shown in FIG. 8 are formed in the scribing region. When thealignment marks 40 are checked after the capacitors Q are formed inaccordance with the steps shown in the first embodiment, traces 41 suchas swellings are found in a part of the alignment marks 40. In thiscase, the alignment mark 40 shown in FIG. 8 consists of a plurality oflayers constituting the capacitor Q.

[0266] Hence, when a cross section of the alignment mark 40, in whichthe swelling seems to be generated, is watched by SEM, a clearance isformed between the oxygen-barrier metal layer 11, which is made ofiridium, and the first interlayer insulating layer 8, as shown in FIG.9.

[0267] Accordingly, in the memory cell region of the semiconductordevice, adherence between the oxygen-barrier metal layer 11 and thefirst interlayer insulating layer 8 must be enhanced much more. In thiscase, adherence between the second and third conductive plugs 10 b, 10 cand the oxygen-barrier metal layer 11 is good.

[0268] Therefore, in the present embodiment, a structure for improvingadhesiveness between the oxygen-barrier metal layer 11 and the firstinterlayer insulating layer 8 and steps of forming the same will beexplained hereunder.

[0269]FIGS. 10A to 10I are sectional views showing steps ofmanufacturing a semiconductor device according to a sixth embodiment ofthe present invention.

[0270] First, as shown in FIG. 10A, in compliance with the steps shownin the first embodiment, the MOS transistors T₁, T₂ are formed on thesilicon substrate 1, and then the cover layer 7, the first interlayerinsulating layer 8, and the first to third conductive plugs 10 a to 10 care formed. In this case, the first interlayer insulating layer 8 is asilicon oxide layer formed by using TEOS as the source gas, for example.

[0271] Then, as shown in FIG. 10B, a titanium (Ti) layer having athickness of more than 5 nm but less than 20 nm, for example, 10 nm, isformed as a conductive adhesion layer 37 on the first to thirdconductive plugs 10 a to 10 c and the first interlayer insulating layer8 by the sputter. In this case, as the conductive adhesion layer 37, asingle-layer structure of the titanium nitride (TiN) layer or adouble-layered structure consisting of a TiN upper layer and a Ti lowerlayer may be employed.

[0272] Then, the iridium layer is formed as the conductiveoxygen-barrier metal layer 11 on the conductive adhesion layer 37 by thesputter. As explained in the first embodiment, the oxygen-barrier metallayer 11 is formed to have a thickness enough to prevent the abnormaloxidation of the second and third conductive plugs 10 b, 10 c.

[0273] Then, as shown in FIG. 10C, the oxygen-barrier metal layer 11 andthe conductive adhesion layer 37 are left like the island on the secondand third conductive plugs 10 b, 10 c and their peripheral areas byetching the oxygen-barrier metal layer 11 and the conductive adhesionlayer 37 while using the same mask (not shown) as the first embodiment.Thus, the first conductive plug 10 a is exposed. Then, the masks areremoved.

[0274] Then, as shown in FIG. 10D, the SiON layer or the Si₃N₄ layer of100 nm thickness, for example, is formed as the oxidation-preventinginsulating layer 12 on the oxygen-barrier metal layer 11, the conductiveadhesion layer 37, and the first interlayer insulating layer 8 by theCVD method. Then, the insulating adhesion layer 13 is formed on theoxidation-preventing insulating layer 12. As the insulating adhesionlayer 13, the SiO₂ layer of 100 nm thickness, for example, is formed bythe CVD method using TEOS, for example.

[0275] Then, as shown in FIG. 10E, the upper surface of theoxygen-barrier metal layer 11 is exposed by polishing the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12 bymeans of the CMP method while causing the oxygen-barrier metal layer 11to function as the stopper layer. In this state, since the conductiveadhesion layer 37 is covered with the oxygen-barrier metal layer 11 andthe oxidation-preventing insulating layer 12, the oxidation of theconductive adhesion layer 37 is prevented.

[0276] Then, as shown in FIG. 10F, the first conductive layer 14 isformed on the oxygen-barrier metal layer 11, the oxidation-preventinginsulating layer 12, and the insulating adhesion layer 13. As shown inthe first embodiment, as the first conductive layer 14, for example, theIr layer 14 w, the IrO₂ layer 14 x, the PtO layer 14 y, and the Pt layer14 z are formed in sequence by the sputter. In this case, the insulatingadhesion layer 13 is annealed to prevent the peeling-off of the layer,for example, before or after the first conductive layer 14 is formed.

[0277] Then, as shown in the first embodiment, the ferroelectric layer15 is formed on the first conductive layer 14. Then, the ferroelectriclayer 15 is crystallized by two-step annealing in the oxygen-containingatmosphere under the same conditions as the first embodiment.

[0278] Then, like the first embodiment, the second conductive layer 16is formed on the ferroelectric layer 15 by the sputter method.

[0279] Then, the hard masks 17 each having the planar shape of thecapacitor are formed on the second conductive layer 16.

[0280] Then, the capacitors Q are formed on the oxygen-barrier metallayer 11, the insulating adhesion layer 13, and the oxidation-preventinginsulating layer 12 by etching in sequence the second conductive layer16, the ferroelectric layer 15, and the first conductive layer 14 in theregion that is not covered with the hard masks 17.

[0281] As shown in FIG. 10G, each of the capacitors Q consists of thelower electrode 14 a made of the first conductive layer 14, thedielectric layer 15 a made of the ferroelectric layer 15, and the upperelectrode 16 a made of the second conductive layer 16. Then, in order torecover the damage of the ferroelectric layer 15 caused by the etching,the recovery annealing is carried out.

[0282] In this manner, when the annealing process such as the recoveryannealing or the like is applied immediately after the patterning of theferroelectric layer 15 is executed, the thermal resistance of the secondand third conductive plugs 10 b, 10 c formed directly under the lowerelectrodes 14 a is decided by the oxygen permeability of theoxygen-barrier metal layers 11, and the oxidation resistance of thefirst conductive plug 10 a not positioned directly under the lowerelectrodes 14 a is decided by the oxygen permeability of the insulatingadhesion layer 13 and the oxidation-preventing insulating layer 12.

[0283] In the annealing process in the above oxygen atmosphere, theconductive adhesion layer 37 covered with the oxidation-preventinginsulating layer 12 and the oxygen-barrier metal layers 11 is notoxidized and thus increase of the resistance of the conductive adhesionlayer 37 is suppressed. Also, the oxidation of the first conductive plug10 a is prevented by the oxidation-preventing insulating layer 12. Inaddition, the abnormal oxidization of the second and third conductiveplugs 10 b, 10 c is prevented by the iridium constituting theoxygen-barrier metal layers 11 and the first conductive layer 14.

[0284] Then, as shown in FIG. 10H, the capacitor protection layer 18 isformed on the capacitors Q and the insulating adhesion layer 13 by thesputter. Then, the capacitors Q are annealed in the oxygen atmosphere.Then, the second interlayer insulating layer 19 is formed on thecapacitor protection layer 18 by the plasma CVD method. Then, the uppersurface of the second interlayer insulating layer 19 is planarized bythe CMP method.

[0285] Then, as shown in FIG. 10I, in compliance with the same steps asthe first embodiment, the capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, theconductive pad 24 a, the first-layer metal wirings 24 b, 24 c, the thirdinterlayer insulating layer 25, the fifth conductive plug 26, the bitline 27, etc. are formed. In this case, in FIG. 10I, the same symbols asthose in FIG. 2O denote the same elements.

[0286] As described above, according to the present embodiment, sincethe conductive adhesion layer 37 is formed of the material that has goodadhesiveness to both the oxygen-barrier metal layers 11 and the firstinterlayer insulating layer 8, the clearance is never generated underthe island-like the oxygen-barrier metal layers 11. If the clearance isgenerated under the island-like oxygen-barrier metal layers 11, it ispossible that the second and third conductive plugs 10 b, 10 c areoxidized through the clearance.

[0287] In addition, by employing the Ti layer as the conductive adhesionlayer 37, orientation strength of a (111) face of the oxygen-barriermetal layers 11 is enhanced. Thus, orientation strength of a (111) faceof the first conductive layer 14 formed on the oxygen-barrier metallayers 11 also is enhanced, and also crystallinity of the ferroelectriclayer 15 formed on the first conductive layer 14 is improved.

[0288] Also, when the alignment marks formed on the scribing lines ofthe silicon substrate (wafer) 1 were checked, no trace of the swellingwas generated and no clearance was found under the iridium layerconstituting the alignment marks.

[0289] In the meanwhile, in the above fifth embodiment, in the case ofwhich the oxygen-barrier metal layers 31 each having the double-layeredstructure consisting of the Ir lower layer 31 a and the IrO₂ upper layer31 b are formed like the island on the second and third conductive plugs10 b, 10 c and their peripheral areas, this conductive adhesion layer 37may be formed between the oxygen-barrier metal layers 31 and the firstinterlayer insulating layer 8.

[0290] More particularly, as shown in FIG. 11, the island-likeoxygen-barrier metal layers 31 may be formed on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas via theisland-like conductive adhesion layer 37. Hence, the peeling-off of theoxygen-barrier metal layers 31 formed on the second and third conductiveplugs 10 b, 10 c is prevented. In this case, the conductive adhesionlayers 37 formed under the oxygen-barrier metal layers 31 are coveredwith the oxygen-barrier metal layers 31 and the oxidation-preventinginsulating layer 12, the oxidation of the conductive adhesion layers 37during the annealing to form the capacitors is prevented.

[0291] (Seventh Embodiment)

[0292] As shown in the second embodiment, by adopting a size of theisland-like oxygen-barrier metal layers 11 a set equal to the capacitorlower electrodes 14 a, the adhesiveness between the oxygen-barrier metallayers 11 a, which is formed to prevent the oxidation of tungstenconstituting the second and third conductive plugs 10 b, 10 c, and thefirst interlayer insulating layer 8 must be improved much more.

[0293]FIGS. 12A to 12G are sectional views showing steps ofmanufacturing a semiconductor device according to a seventh embodimentof the present invention.

[0294] Next, steps required until a structure shown in FIG. 12A isformed will be explained hereunder.

[0295] First, in compliance with the steps shown in the firstembodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1, and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed.

[0296] Then, the titanium (Ti) layer is formed as the conductiveadhesion layer 37 on the first to third conductive plugs 10 a to 10 cand the first interlayer insulating layer 8 by the sputter. It ispreferable that a thickness of the titanium layer should be set to keepconductivity of the titanium layer if the titanium layer is oxidized,and the thickness is set to more than 5 nm but less than 20 nm, forexample, 10 nm. As the conductive adhesion layer 37, the single-layerstructure of the TiN layer or the double-layered structure consisting ofthe TiN upper layer and the Ti lower layer may be employed.

[0297] Then, the iridium layer of 400 nm thickness is formed as theconductive oxygen-barrier metal layer 11 a on the conductive adhesionlayer 37 by the sputter. The oxygen-barrier metal layer 11 a constitutesa part of the lower electrode of the capacitor Q, as described later.

[0298] Then, the hard masks made of titanium nitride, silicon oxide, orthe like are formed as the masks M₂ on the oxygen-barrier metal layer 11a over the second and third conductive plugs 10 b, 10 c and theirperipheral areas. The planar shape of the masks M₂ are set equal to theshape of the lower electrode of the capacitor, to be described later.

[0299] Then, as shown in FIG. 12B, the oxygen-barrier metal layer 11 aand the conductive adhesion layer 37 are etched in the region that isnot covered with the masks M₂. Thus, the oxygen-barrier metal layer 11 aand the conductive adhesion layer 37 are left on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas to have the sizeof the capacitor. Here, the first conductive plug 10 a is exposed. Then,the masks M₂ are removed.

[0300] Then, as shown in FIG. 12C, the oxidation-preventing insulatinglayer 12 and the insulating adhesion layer 13 are formed in sequence onthe oxygen-barrier metal layer 11 a, the conductive adhesion layer 37,the first conductive plug 10 a, and the first interlayer insulatinglayer 8 under the same conditions as the second embodiment.

[0301] Then, as shown in FIG. 12D, the upper surface of theoxygen-barrier metal layer 11 a is exposed by polishing theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 by means of the CMP method while causing the oxygen-barriermetal layer 11 a to function as the stopper layer. Hence, upper surfacesof the oxygen-barrier metal layer 11 a, the insulating adhesion layer13, and the oxidation-preventing insulating layer 12 are made flatsubstantially.

[0302] Then, as shown in FIG. 12E, like the second embodiment, the IrO₂layer 14 x of 30 nm thickness, the PtO layer 14 y of 30 nm thickness,and the Pt layer 14 z of 50 nm thickness, for example, are formedsequentially as the first conductive layer 14 b on the oxygen-barriermetal layer 11 a, the oxidation-preventing insulating layer 12, and theinsulating adhesion layer 13 by the sputter. In this case, theinsulating adhesion layer 13 is annealed to prevent the peeling-off ofthe layer before or after the first conductive layer 14 b is formed.

[0303] Then, the ferroelectric layer 15 is formed on the firstconductive layer 14 under the conditions shown in the second embodiment.Then, the ferroelectric layer 15 is annealed in the oxygen-containingatmosphere to crystallize. As shown in the second embodiment, two-stepRTA process is employed as such annealing. Then, the IrO₂ layer of 200nm thickness, for example, is formed as the second conductive layer 16on the ferroelectric layer 15 by the sputter method.

[0304] Then, the TiN layer and the SiO₂ layer are formed sequentially onthe second conductive layer 16, and then the hard masks 17 are formed bypatterning these layers. each having the planar shape of the capacitor.The hard masks 17 are patterned into the capacitor shape, which isalmost similar to the oxygen-barrier metal layer 11 a, over the secondand third conductive plugs 10 b, 10 c.

[0305] Then, the second conductive layer 16, the ferroelectric layer 15,and the first conductive layer 14 b in the region, which is not coveredwith the hard masks 17, are etching in sequence under the sameconditions as the second embodiment. Then, the hard masks 17 areremoved.

[0306] With the above, as shown in FIG. 12F, the capacitors Q are formedon the first interlayer insulating layer 8. The lower electrode 14 a ofthe capacitor Q is made of the first conductive layer 14 b and theoxygen-barrier metal layer 11 a. Also, the dielectric layer 15 a of thecapacitor Q is made of the ferroelectric layer 15, and the upperelectrode 16 a of the capacitor Q is made of the second conductive layer16.

[0307] After this, as shown in FIG. 12G, in compliance with the samesteps as the second embodiment, the capacitor protection layer 18, thesecond interlayer insulating layer 19, the fourth conductive plug 21,the conductive pad 24 a, the first-layer metal wirings 24 b, 24 c, thethird interlayer insulating layer 25, the fifth conductive plug 26, thebit line 27, etc. are formed. In this case, in FIG. 12G, the samesymbols as those in FIG. 3I denote the same elements.

[0308] As described above, according to the present embodiment, sincethe conductive adhesion layer 37 is formed of that material that hasgood adhesiveness to both the oxygen-barrier metal layers 11 a and thefirst interlayer insulating layer 8, the clearance is never generatedunder the oxygen-barrier metal layers 11 a constituting the lowerelectrode 14 a of the capacitor Q. In addition, by adopting the Ti layeras the conductive adhesion layer 37, the orientation strength of the(111) face of the lower electrode 14 a is enhanced. Thus, thecrystallinity of the ferroelectric layer 15 is improved.

[0309] By the way, as shown in the fourth embodiment, in the structurein which the island-like oxygen-barrier metal layer 11 a is formed onnot only the second and third conductive plugs 10 b, 10 c and theirperipheral areas but also the first conductive plug 10 a and itsperipheral area, the conductive adhesion layer 37 may be formed betweenthe first interlayer insulating layer 8 and the island-likeoxygen-barrier metal layers 11 a around the first conductive plug 10 aand its peripheral area.

[0310] Accordingly, as shown in FIG. 13, the clearance is never formedunder the island-like oxygen-barrier metal layers 11 a that are formedon not only the second and third conductive plugs 10 b, 10 c but alsothe first conductive plug 10 a. As a result, the first to thirdconductive plugs 10 a to 10 c are not oxidized in the annealing in theoxygen atmosphere. If the clearance is generated under the island-likeoxygen-barrier metal layers 11 a, it is possible that the first to thirdconductive plugs 10 a to 10 c are oxidized through the clearance.

[0311] (Eighth Embodiment)

[0312] In the above embodiment, the steps of patterning theoxygen-barrier metal layers 11 or 11 a to leave on the second and thirdconductive plugs 10 b, 10 c and their peripheral areas like the island.The hard masks M₁, M₂ may be employed upon patterning the oxygen-barriermetal layers 11 or 11 a.

[0313] In the condition of which titanium nitride is employed as thematerial of the hard masks M₁, M₂, it may be considered that, since thehard masks are formed as the conductive mask, such hard masks are notremoved to leave as it is after the patterning of the oxygen-barriermetal layers 11 or 11 a. However, the titanium nitride is oxidized bythe oxygen annealing, which is applied to form the capacitor, and thusits resistance is increased higher. Hence, it is not preferable to leavethe titanium nitride as it is. Therefore, after the oxygen-barrier metallayers 11 or 11 a are patterned, the hard masks M₁, M₂ made of titaniumnitride are removed by the wet etching using ammonium peroxide, forexample.

[0314] However, as explained in the first and second embodiments, afterthe oxygen-barrier metal layers 11 or 11 a are patterned, a part of boththe tungsten layer 9 b constituting the first conductive plug 10 a andthe glue layer 9 a made of titanium nitride/titanium is exposed from thefirst interlayer insulating layer 8. Therefore, since the titaniumnitride constituting the first conductive plug 10 a is also etchedsimultaneously when the hard masks M₁, M₂ made of titanium nitride areremoved, a recess is generated in the first conductive plug 10 a. Sincethe insulating material is filled in the recess, it is possible toincrease the resistance of the first conductive plug 10 a.

[0315] As a result, in the present embodiment, memory cell forming stepsof employing a new method of removing the hard masks after thepatterning of the oxygen-barrier metal layers 11 or 11 a will beexplained hereunder.

[0316]FIGS. 14A to 14G are sectional views showing steps ofmanufacturing a semiconductor device according to an eighth embodimentof the present invention.

[0317] Next, steps required until a structure shown in FIG. 14A isformed will be explained hereunder.

[0318] First, in compliance with the steps shown in the firstembodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1, and then the cover layer 7, the first interlayer insulatinglayer 8, and the first to third conductive plugs 10 a to 10 c areformed. After this, the first interlayer insulating layer 8 is exposedto the nitrogen plasma atmosphere at the substrate temperature of 350°C. for 120 second.

[0319] Then, as shown in FIG. 14B, the iridium layer is formed as theconductive oxygen-barrier metal layer 11 on the first to thirdconductive plugs 10 a to 10 c and the first interlayer insulating layer8 by the sputter. The iridium layer is formed to have a thickness of 200nm, for example.

[0320] Then, masks M₃ made of titanium nitride are formed on theoxygen-barrier metal layer 11 over the second and third conductive plugs10 b, 10 c and their peripheral areas. A titanium nitride (TiN) layer of200 nm thickness is formed on the oxygen-barrier metal layer 11 and thenis left as the masks M₃ on the second and third conductive plugs 10 b,10 c and their peripheral areas by etching the TiN layer while usingresist patterns (not shown). In this case, the TiN layer is etched byusing BCl₃ and Cl₂. Then, the resist patterns are removed.

[0321] Then, as shown in FIG. 14C, the oxygen-barrier metal layer 11 isetched in the region that is not covered with the masks M₃. Thus, theoxygen-barrier metal layer 11 is left like the island on the second andthird conductive plugs 10 b, 10 c and their peripheral areas. The firstconductive plug 10 a is exposed by the etching of the oxygen-barriermetal layer 11.

[0322] The etching of the oxygen-barrier metal layer 11 made of iridiumis executed by using the ICP plasma etching equipment. The electricpower of 800 W is applied to the coil antenna arranged at the upperportion in the chamber of the ICP plasma etching equipment, and the biaspower of 700 W is applied to the stage on which the wafer is loaded inthe chamber. Also, the pressure in the chamber is set to 0.4 Pa, and thestage temperature is set to 400° C. Also, as the etching gas of theoxygen-barrier metal layer 11, HBr and O₂ are introduced into thechamber at flow rates of 10 sccm and 40 sccm respectively. Also, afterthe etching of the oxygen-barrier metal layer 11 is completed, theover-etching is carried out for a time, a length of which is equal tothe etching time, not to leave the oxygen-barrier metal layer 11 in theregion except the second and third conductive plugs 10 b, 10 c and theirperipheral areas.

[0323] Then, as shown in FIG. 14D, the SiON layer or the Si₃N₄ layer of100 nm thickness, for example, is formed as the oxidation-preventinginsulating layer 12 on the masks M₃, the oxygen-barrier metal layer 11,the first interlayer insulating layer 8, and the first conductive plug10 a by the CVD method. Then, the insulating adhesion layer 13 is formedon the oxidation-preventing insulating layer 12. As the insulatingadhesion layer 13, the SiO₂ layer of 100 nm thickness is formed by theCVD method using TEOS, for example.

[0324] Then, as shown in FIG. 14E, the insulating adhesion layer 13, theoxidation-preventing insulating layer 12, and the masks M₁ are polishedby the CMP method while causing the oxygen-barrier metal layer 11 tofunction as the stopper layer. Hence, the masks are removed and an uppersurface of the oxygen-barrier metal layer 11 is exposed. In this case,the upper surfaces of the oxygen-barrier metal layer 11, the insulatingadhesion layer 13, and the oxidation-preventing insulating layer 12 aremade flat substantially.

[0325] This CMP method is executed by using the polishing machine. Also,a product name IC1010 manufactured by Rodel Nitta Company, for example,is used as the abrasive cloth, and SS-25E manufactured by CabbotCorporation, for example, is used as the slurry. The polishing time is70 second, for example.

[0326] Then, as shown in FIG. 14F, in compliance with the steps shown inthe first embodiment, the capacitors Q are formed on theoxidation-preventing insulating layer 12, and the insulating adhesionlayer 13 on the island-like oxygen-barrier metal layers 11. Thecapacitor Q consists of the lower electrode 14 a, the ferroelectriclayer 15 a, and the upper electrode 16 a. The lower electrode 14 a isconnected to the conductive plug 10 b (10 c) via the island-likeoxygen-barrier metal layer 11.

[0327] After this, as shown in FIG. 14G, in compliance with the samesteps as the first embodiment, the capacitor protection layer 18, thesecond interlayer insulating layer 19, the fourth conductive plug 21,the conductive pad 24 a, the first-layer metal wirings 24 b, 24 c, thethird interlayer insulating layer 25, the fifth conductive plug 26, thebit line 27, etc. are formed. In this case, in FIG. 14G, the samesymbols as those in FIG. 2O denote the same elements.

[0328] As described above, according to the present invention, theoxygen-barrier metal layer 11 is patterned by using the masks M₃ formedover the second and third conductive plugs 10 b, 10 c, then theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are formed on the masks M₃, the first interlayer insulatinglayer 8, and the first conductive plug 10 g without removal of the masksM₃, and then the masks M₃ are removed by the polishing executed when theoxidation-preventing insulating layer 12 and the insulating adhesionlayer 13 are to be polished.

[0329] Therefore, TiN constituting the glue layer 9 a of the firstconductive plug 10 a is not etched in removing the masks M₃. As aresult, the first conductive plug 10 a does not suffer damage inremoving the masks M₃, and thus the first conductive plug 10 a togetherwith the second and third conductive plugs 10 b, 10 c connect theimpurity diffusion region 5 a to the bit line 27 on a via-to-via basis.In addition, the independent step of removing the masks M₃ only isomitted and thus throughput is improved.

[0330] In the meanwhile, as set forth in Patent Application Publication(KOKAI) Hei 11-126778, if the masks M₃ is removed by the CMP method inthe state shown in-FIG. 14C immediately after the oxygen-barrier metallayer 11 is patterned, the moisture enters into the surface of the firstinterlayer insulating layer 8 to cause the first conductive plug 10 a tooxidize. Therefore, such situation is not preferable.

[0331] In this case, material of the masks M₃ employed to pattern theoxygen-barrier metal layer 11 is not limited to titanium nitride. Thedouble-layered structure obtained by forming titanium nitride (TiN) andsilicon oxide (SiO₂) sequentially may be employed, or such masks may beformed of other material.

[0332] (Ninth Embodiment)

[0333] Like the eighth embodiment, removal of the mask M₂ shown in thesecond embodiment may be executed at the same time when theplanarization of the oxidation-preventing insulating layer 12 and theinsulating adhesive layer 13 is executed by the CMP method after theoxidation-preventing insulating layer 12 and the insulating adhesivelayer 13 are formed on the mask M₂ and the first interlayer insulatinglayer 8.

[0334] Therefore, steps of forming a hard mask having a double-layeredstructure consisting of a TiN layer and an SiO₂ layer as a mask used topattern an oxygen-barrier metal layer 11 a and then removing such hardmask by the CMP method will be explained hereunder.

[0335]FIGS. 15A to 15D are sectional views showing steps ofmanufacturing a semiconductor device according to a ninth embodiment ofthe present invention, which are taken along a I-I line in a plan viewof the memory cell region shown in FIG. 17. That is, FIGS. 15A to 15Dshow steps of forming the island-like oxygen-barrier metal layer 11 aunder the capacitor Q, which is formed on one side of one p-type well 1a, and two capacitors Q, which are positioned adjacently to each otherin the extending direction of the gate electrodes (word lines) 4 a, 4 b,respectively.

[0336] Steps required until a structure shown in FIG. 15A is formed willbe explained hereunder.

[0337] First, in compliance with the steps shown in the firstembodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1, and then the cover layer 7 for covering the MOS transistorsT₁, T₂, the first interlayer insulating layer 8, the first to thirdconductive plugs 10 a to 10 c are formed sequentially. Then, the firstinterlayer insulating layer 8 is exposed to the nitrogen plasmaatmosphere at the substrate temperature of 350° C. for 120 sec.

[0338] Then, the iridium (Ir) layer is formed as the conductiveoxygen-barrier metal layer 11 a on the first to third conductive plugs10 a to 10 c and on the first interlayer insulating layer 8 by thesputter. The Ir layer is formed to have a thickness of 400 nm, forexample.

[0339] Then, a TiN layer 51 of 200 nm thickness is formed on theoxygen-barrier metal layer 11 a by the sputter method. Then, an SiO₂layer 52 of 1000 nm thickness is formed on the TiN layer 51 by the CVDmethod using TEOS.

[0340] Then, a resist is coated on the SiO₂ layer 52, and then resistpatterns 53 each having an almost capacitor planar shape are formed overthe second and third conductive plugs 10 b, 10 c and their peripheralareas by exposing/developing the resist. Then, areas of the SiO₂ layer52 and the TiN layer 51, which are not covered with the resist pattern53, are etched. Thus, the SiO₂ layer 52 and the TiN layer 51 being leftunder the resist patterns 53 are used as a first hard mask 50.

[0341] Then, the resist patterns 53 are removed by the oxygen ashing.

[0342] Then, as shown in FIG. 15B, areas of the oxygen barrier metallayer 11 a, which are not covered with the first hard mask 50, areetched. Thus, the oxygen-barrier metal layer 11 a is left like an islandon the second and third conductive plugs 10 b, 10 c and their peripheralareas. The oxygen-barrier metal layer 11 a is patterned by the dryetching using a mixed gas of HBr, O₂, and C₄F₈ while setting thetemperature of the stage, on which the silicon substrate 1 is loaded, to400° C. In this case, the SiO₂ layer 52 constituting the first hard mask50 is also etched into an almost cone shape at the time of such etching.

[0343] Then, as shown in FIG. 15C, a silicon oxide nitride (SiON) layeror a silicon nitride (Si₃N₄) layer of 350 nm thickness is formed as anoxidation-preventing insulating layer 54 on the first hard mask 50, theoxygen-barrier metal layer 11 a, and the first interlayer insulatinglayer 8 by the CVD method. The SiON layer is formed by the CVD methodusing silane, ammonia, and oxygen, for example. Also, the Si₃N₄ layer isformed by the CVD method using silane and ammonia, for example.

[0344] Then, an SiO₂ layer of 600 nm thickness is formed as a sacrificeoxide layer 55 on the oxidation-preventing insulating layer 54 by theCVD method using TEOS as the growth gas. In this case, in the presentembodiment, the insulating adhesive layer formed in the aboveembodiments is not formed on the oxidation-preventing insulating layer.

[0345] Then, as shown in FIG. 15B, the sacrifice oxide layer 55, theoxidation-preventing insulating layer 54, and the first hard mask 50 arepolished by the CMP method while causing the island-like oxygen-barriermetal layer 11 a to act as a stopper layer. Thus, the first hard mask 50is removed and thus an upper surface of the oxygen-barrier metal layer11 a is exposed. Then, the oxidation-preventing insulating layer 54 isleft on the first interlayer insulating layer 8 and the first conductiveplug 10 a on the side of the island-like oxygen-barrier metal layer 11a. Also, the thin sacrifice oxide layer 55 is left on theoxidation-preventing insulating layer 54. In this case, upper surfacesof the oxygen-barrier metal layer 11 a, the oxidation-preventinginsulating layer 54, and the sacrifice oxide layer 55 are madesubstantially flat. The abrasive cloth and the slurry shown in theeighth embodiment are employed at the time of such polishing.

[0346] Then, the capacitors are formed by the steps shown in the secondembodiment, but their details will be omitted herein.

[0347] As described above, the first hard mask 50 used only for thepatterning of the island-like oxygen-barrier metal layer 11 a, which isused as a part of the capacitor lower electrode, is removed at the timeof the planarization of the oxidation-preventing insulating layer 54.Therefore, like the eighth embodiment, the isolated step of removingonly the first hard mask 50 is eliminated.

[0348] Meanwhile, if an interval between the capacitors, which arearranged adjacently in the extending direction of the gate electrodes(word lines) 4 a, 4 b, is narrow such as about 1 μm and theoxygen-barrier metal layer 11 a is thick such as about 400 nm, forexample, an aspect ratio of a space between the island-likeoxygen-barrier metal layers 11 a and the first hard masks 50 becomeslarge, as shown in FIG. 15C. Thus, the space is not perfectly buried bythe oxidation-preventing insulating layer 54, and thus a narrowclearance 54 s is generated in the oxidation-preventing insulating layer54. Since the oxidation-preventing insulating layer 54 becomes thinunder the clearance 54 s, the following disadvantage is caused in thelater capacitor forming steps.

[0349] In this case, if the interval between the capacitors Q shown inFIG. 17 is wide, the clearance 54 s shown in FIG. 15C is not generated.Hence, there is caused no trouble to execute both the removal of thefirst hard masks 50 having the double-layered structure and theplanarization of the oxidation-preventing insulating layer 54simultaneously by the CMP method.

[0350] Therefore, the capacitor forming steps executed after the firsthard masks 50 is removed will be explained simply hereunder.

[0351] First, as shown in FIG. 16A, a first conductive layer 14 b isformed on the island-like oxygen-barrier metal layer 11 a, theoxidation-preventing insulating layer 54, and the sacrifice oxide layer55. As the first conductive layer 14 b, a laminated structure unlike thesecond embodiment is formed. For example, an Ir layer 14 w of 30 nmthickness, an IrO₂ layer 14 x of about 30 nm thickness, a Pt layer 14 vof 15 nm thickness, a PtO layer 14 y of about 25 nm thickness, and a Ptlayer 14 z of about 50 nm thickness are formed sequentially by thesputter.

[0352] In this case, the oxidation-preventing insulating layer 54 isannealed in the argon atmosphere to prevent the peeling-off of thelayer, for example, before or after the formation of the firstconductive layer 14 b.

[0353] Then, a ferroelectric layer 15 and a second conductive layer 16are formed on the first conductive layer 14 b. As the ferroelectriclayer 15, a PZT layer of 140 to 200 nm thickness is formed by thesputter method. Then, the ferroelectric layer 15 is annealed in theoxygen atmosphere to crystallize the ferroelectric layer 15. In thiscase, as the growth method and the material of the ferroelectric layer15, the growth method and the material shown in the second embodimentmay be employed in addition to this.

[0354] Then, a TiN layer 56 of 200 nm thickness is formed on the secondconductive layer 16 by the PVD method. Then, an SiO₂ layer 57 of 900 nmthickness is formed on the TiN layer 56 by the CVD method using TEOS.

[0355] Then, a resist is coated on the SiO₂ layer 57. Then, resistpatterns 59 each having an almost capacitor planar shape are formed overthe second and third conductive plugs 10 b, 10 c and their peripheralareas by exposing/developing the resist. Then, areas of the SiO₂ layer57 and the TiN layer 56, which are not covered with the resist pattern59, are etched. Thus, the SiO₂ layer 57 and the TiN layer 56 being leftunder the resist patterns 59 are used as a second hard mask 58. In thiscase, the SiO₂ layer 57 is etched by using a mixed gas of C₄F₈, Ar, andCF₄. Also, the TiN layer 56 is etched by using a mixed gas of BCl₃ andCl₂, or other gas.

[0356] Then, the resist patterns 59 are removed by the oxygen ashing.

[0357] Then, as shown in FIG. 16B, the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b in areasthat are not covered with the second hard mask 58 are etchedsequentially. In this case, all the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b are etchedby using the ICP plasma etching equipment. The substrate temperature atthe time of etching is set to 400° C. Also, a mixed gas consisting ofHBr and O₂ is used as the etching gas for the first conductive layer 14b and the second conductive layer 16. Also, a mixed gas consisting ofCl₂ and Ar is used as the etching gas for the ferroelectric layer 15.

[0358] Thus, the capacitors Q connected to the second and thirdconductive plugs 10 b, 10 c respectively are formed on the firstinterlayer insulating layer 8. The lower electrode 14 a of the capacitorQ is constructed by the first conductive layer 14 b and theoxygen-barrier metal layer 11 a. Also, the dielectric layer 15 a of thecapacitor Q is constructed by the ferroelectric layer 15, and the upperelectrode 16 a of the capacitor Q is constructed by the secondconductive layer 16.

[0359] In this case, the SiO₂ layer 57 constituting the second hard mask58 is also etched into an almost cone shape at the time of such etching.

[0360] Then, as shown in FIG. 16C, the SiO₂ layer 57 constituting thesecond hard mask 58 is removed by the two-frequency reactive ion etching(two-frequency RIE) method using a mixed gas of C₄F₈, Ar, and O₂. At thetime of etching of the SiO₂ layer 57, the oxidation-preventinginsulating layer 54 consisting of the SiON layer and the Si₃N₄ layerfunctions as the etching stopper layer. Then, the TiN layer 56 of thesecond hard mask 58 is removed by the wet etching using a mixed chemicalconsisting of hydrogen peroxide and ammonia.

[0361] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching, the recovery annealing of the capacitor Q isexecuted. The recovery annealing in this case is executed at thesubstrate temperature of 650° C. for 60 min in the atmosphere containingthe oxygen, for example.

[0362] Then, steps goes to the steps of forming the second interlayerinsulating layer, etc. like the above embodiments, but their detailswill be omitted herein.

[0363] By the way, as shown in FIG. 15C, if the interval between thepatterns each of which is composed of the island-like oxygen-barriermetal layer 11 a and the first hard mask 50 becomes narrow, theclearance 54 s is formed in the oxidation-preventing insulating layer 54formed between such patterns. Thus, as shown in FIG. 16B, a thickness ofthe oxidation-preventing insulating layer 54 is reduced when the secondconductive layer 16, the ferroelectric layer 15, and the firstconductive layer 14 b are etched, and thus the first interlayerinsulating layer 8 is etched through the clearance 54 s to generate anconcave portion. In addition, a depth of such concave portion isincreased much more through the clearance 54 s when the SiO₂ layer 57 ofthe second hard mask 58 is removed.

[0364] If the depth of such concave portion in the first interlayerinsulating layer 8 is increased, the oxygen enters into the firstinterlayer insulating layer 8 from the concave portion during therecovery annealing executed after the patterning of the capacitors Q,and then the oxygen penetrates through the first interlayer insulatinglayer 8. Thus, the second and third conductive plugs 10 b, 10 c made oftungsten are oxidized, and further the MOS transistors T1, T2 aredeteriorated.

[0365] On the contrary, it may be thought of that the aspect ration ofthe space between the island-like oxygen barrier metal layers 11 a isreduced by thinning the oxygen-barrier metal layer 11 a to prevent thegeneration of the clearance 54 s.

[0366] However, the selective etching ratio of the SiO₂ layer 52constituting the first hard mask 50 is small such as about 5 to 7 incomparison with the SiON layer or the Si₃N₄ layer constituting theoxidation-preventing insulating layer 54 made of SiO₂. Therefore, theoxidation-preventing insulating layer 54 as well as the first hard mask50 is etched during the etching of the first hard mask 50, and thus athickness of the oxidation-preventing insulating layer 54 is reduced byabout 150 nm. In addition, the thickness of the oxidation-preventinginsulating layer 54 is also reduced by about 100 nm by the overetchingthat is caused subsequently to the formation of the capacitors Q. Incontrast, in order to prevent the oxidation of the first conductive plug10 a by the oxidation-preventing insulating layer 54, the thickness ofthe oxidation-preventing insulating layer 54 needs about 100 nm with asmall margin.

[0367] Therefore, the thickness of the oxidation-preventing insulatinglayer 54 must be formed thick to leave 350 nm after the polishing of theoxidation-preventing insulating layer 54. If the thickness of theoxidation-preventing insulating layer 54 is set to 350 nm, a thicknessof the oxygen-barrier metal layer 11 a must be set to 350 nm or morewith regard to the polishing of the oxidation-preventing insulatinglayer 54 by the CMP method.

[0368] In this case, in the first to eighth embodiments, respectivethicknesses of the oxidation-preventing insulating layer 12 and theinsulating adhesive layer 13 are given by the values obtained in thecondition that reduction in thicknesses of such layers are seldomconsidered.

[0369] With the above, if the interval between the capacitors Q isnarrowed rather than 1 μm, for example, it is not preferable that theremoval of the first hard mask 50 made of inorganic material and theplanarization of the oxidation-preventing insulating layer 54 shouldexecuted simultaneously.

[0370] Therefore, in a next tenth embodiment, a method of removing thefirst hard mask 50 not to form the concave portion in the firstinterlayer insulating layer 8 between the capacitors Q executed when theinterval between the capacitors Q becomes narrower than 1 μm will beexplained hereunder.

[0371] (Tenth Embodiment)

[0372]FIGS. 18A to 18G are sectional views showing steps ofmanufacturing a semiconductor device according to a tenth embodiment ofthe present invention, which are taken along a I-I line in FIG. 17.

[0373] Steps required until a structure shown in FIG. 18A is formed willbe explained hereunder.

[0374] First, in compliance with the steps shown in the firstembodiment, the MOS transistors T₁, T₂ are formed on the siliconsubstrate 1, and then the cover layer 7 for covering the MOS transistorsT₁, T₂, the first interlayer insulating layer 8, the first to thirdconductive plugs 10 a to 10 c are formed sequentially. Then, the firstinterlayer insulating layer 8 is exposed to the nitrogen plasmaatmosphere at the substrate temperature of 350° C. for 120 sec.

[0375] Then, the iridium layer is formed as a conductive oxygen-barriermetal layer 11 b on the first to third conductive plugs 10 a to 10 c andon the first interlayer insulating layer 8 by the sputter. The iridiumlayer is formed to have a thickness of 200 nm, for example.

[0376] Then, a TiN layer 60 of 100 nm thickness is formed on theoxygen-barrier metal layer 11 b by the sputter method.

[0377] Then, a resist is coated on the TiN layer 60, and then resistpatterns 61 each having an almost capacitor planar shape are formed overthe second and third conductive plugs 10 b, 10 c and their peripheralareas by exposing/developing the resist. Then, areas of the TiN layer60, which are not covered with the resist pattern 61, are etched. Thus,the TiN layer 60 being left under the resist patterns 61 are used as afirst hard mask 60 a.

[0378] Then, the resist patterns 61 are removed by the oxygen ashing.

[0379] Then, as shown in FIG. 18B, areas of the oxygen barrier metallayer 11 b, which are not covered with the first hard mask 60 a, areetched. Thus, the oxygen barrier metal layer 11 b is left like an islandon the second and third conductive plugs 10 b, 10 c and their peripheralareas. The oxygen-barrier metal layer 11 b is patterned by thehigh-temperature dry etching using a mixed gas of HBr, O₂, and C₄F₈while setting the substrate temperature to 400° C. In this case, theSiO₂ layer 52 constituting the first hard mask 50 is also etched into analmost cone shape at the time of such etching.

[0380] Then, as shown in FIG. 18C, an alumina layer for covering thefirst hard mask 60 a and the oxygen-barrier metal layer 11 b is formedas an oxidation-preventing insulating layer 62 on the first interlayerinsulating layer 8 to have a thickness of 100 to 150 nm. The aluminalayer may be formed either the sputter method or the CVD method. As thecondition that the alumina layer is formed by the MOCVD method, a gas inwhich hydrogen (H₂) or ozone (O₃) is added to trimethylaluminium(Al(CH₃)₃), for example, is employed, and the substrate temperature isset to 300° C., for example.

[0381] Then, an SiO₂ layer of 600 nm thickness is formed as a sacrificeoxide layer 63 on the oxidation-preventing insulating layer 62. Thesacrifice oxide layer 63 is formed by the CVD method using TEOS, forexample.

[0382] Then, as shown in FIG. 18D, the sacrifice oxide layer 63, theoxidation-preventing insulating layer 62, and the first hard mask 60 aare polished by the CMP method while causing the island-likeoxygen-barrier metal layer 11 b to act as the stopper layer. At the timeof such polishing, the abrasive cloth and the slurry shown in the eighthembodiment are employed. Thus, upper surfaces of the oxygen-barriermetal layer 11 a, the oxidation-preventing insulating layer 54, and thesacrifice oxide layer 55 are made substantially flat, and the first hardmask 60 a is removed and thus an upper surface of the underlyingoxygen-barrier metal layer 11 b is exposed. In addition, theoxidation-preventing insulating layer 54 left on the side of theisland-like oxygen-barrier metal layer 11 b covers the first interlayerinsulating layer 8 and the first conductive plug 10 a. In this case, thesacrifice oxide layer 63 is left thin on the oxidation-preventinginsulating layer 62.

[0383] As described above, if the island-like oxygen barrier metal layer11 b is used as a part of the capacitor lower electrode, the first hardmask 60 a is removed from the upper surface of the island-like oxygenbarrier metal layer 11 b by the CMP method subsequently to theoxidation-preventing insulating layer 63. Therefore, like the eighth andninth embodiments, the isolated step of removing only the first hardmask 60 a is eliminated.

[0384] Then, as shown in FIG. 18E, the first conductive layer 14 b isformed on the oxygen-barrier metal layer 11 b, the oxidation-preventinginsulating layer 62, and the sacrifice oxide layer 63. As the firstconductive layer 14 b, the laminated structure unlike the secondembodiment is formed. For example, an Ir layer 14 w of 100 to 200 nmthickness, an IrO₂ layer 14 x of about 30 nm thickness, a Pt layer 14 vof 15 nm thickness, a PtO layer 14 y of about 25 nm thickness, and a Ptlayer 14 z of about 50 nm thickness are formed sequentially.

[0385] In this case, the oxidation-preventing insulating layer 54 isannealed in the argon atmosphere to prevent the peeling-off of thelayer, for example, before or after the formation of the firstconductive layer 14 b.

[0386] Then, the ferroelectric layer 15 and the second conductive layer16 are formed on the first conductive layer 14 b. As the ferroelectriclayer 15, a PZT layer of 140 to 200 nm thickness is formed by thesputter method. Then, the ferroelectric layer 15 is annealed in theoxygen atmosphere to crystallize the ferroelectric layer 15. In thiscase, as the growth method and the material of the ferroelectric layer15, the growth method and the material shown in the second embodimentmay be employed in addition to this.

[0387] Then, an IrO₂ layer of about 200 to 300 nm thickness, forexample, is formed as the second conductive layer 16 on theferroelectric layer 15 by the sputter method.

[0388] Then, a TiN layer 56 of 200 nm thickness is formed on the secondconductive layer 16 by the PVD method using TEOS. Then, an SiO₂ layer 57of 900 nm thickness is formed on the TiN layer 56 by the CVD methodusing TEOS.

[0389] Then, a resist is coated on the SiO₂ layer 57. Then, resistpatterns 59 each having an almost capacitor planar shape are formed overthe second and third conductive plugs 10 b, 10 c and their peripheralareas by exposing/developing the resist. Then, areas of the SiO₂ layer57 and the TiN layer 56, which are not covered with the resist pattern59, are etched. Thus, the SiO₂ layer 57 and the TiN layer 56 being leftunder the resist patterns 59 are used as a second hard mask 58. In thiscase, the TiN layer 56 is etched by using a mixed gas of BCl₃ and Cl₂,or Cl₂ or other gas. Also, the SiO₂ layer 57 is etched by setting thesubstrate temperature to 0 to 20° C. In this case, the dry etching ofthe SiO₂ layer 57 and the TiN layer 56 is executed by exchanging theetcher.

[0390] Then, the resist patterns 59 are removed by the oxygen ashing.

[0391] Then, as shown in FIG. 18F, the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b in areasthat are not covered with the second hard mask 58 are etchedsequentially. In this case, all the second conductive layer 16, theferroelectric layer 15, and the first conductive layer 14 b are etchedby using the ICP plasma etching equipment.

[0392] As these etching conditions, a pressure in the chamber is set to0.4 Pa, the wafer stage temperature is set to 400° C., a source power isset to 800 watt, and a bias power is set to 700 watt. Also, as theetching gas for the second conductive layer 16 and the first conductivelayer 14 b, HBr and O₂ are supplied to the etching chamber at a flowrate of 10 sccm and 40 sccm respectively. Also, as the etching gas forthe ferroelectric layer 15, Cl₂ and Ar are supplied to the etchingchamber at a flow rate of 40 sccm and 10 sccm respectively. In thiscase, the source power is a power of a high-frequency power supplyapplied to an antenna of the ICP plasma etching equipment. The biaspower is a power of a high-frequency power supply applied to thesemiconductor wafer (silicon substrate) 1.

[0393] Thus, a plurality of capacitors Q that are connected to thesecond and third conductive plugs 10 b, 10 c separately are formed onthe first interlayer insulating layer 8. The lower electrode 14 a of thecapacitor Q is constructed by the first conductive layer 14 b and theoxygen-barrier metal layer 11 b. Also, the dielectric layer 15 a of thecapacitor Q is constructed by the ferroelectric layer 15, and the upperelectrode 16 a of the capacitor Q is constructed by the secondconductive layer 16.

[0394] In this case, at the time of such etching, the SiO₂ layer 57constituting the second hard mask 58 is also etched and is left like analmost cone shape.

[0395] Then, as shown in FIG. 18G, the SiO₂ layer 57 constituting thesecond hard mask 58 is removed by the two-frequency reactive ion etching(two-frequency RIE) using a mixed gas consisting of C₄F₈, Ar, and O₂. Atthe time of such etching, for example, a power supply of 2000 W and27.13 MHz is connected to the upper electrode out of the parallel-platetype electrodes in the reaction chamber of the two-frequency RIEequipment and a power supply of 200 W and 800 kHz is connected to thelower electrode thereof. Also, a distance between the lower electrodeand the upper electrode is set to 20 mm. The temperature of the upperelectrode is set to 30° C., and the temperature of the lower electrodeon which the silicon substrate 1 is loaded is set to 0° C. Also, thetemperature of the inner side wall of the reaction chamber is set to 50°C. Also, as the etching gas, C₄F₈, Ar, and O₂ are introduced into thereaction chamber at a flow rate of 20 sccm, 500 sccm, and 8 sccmrespectively. Also, a gas pressure in the reaction chamber is set to 25to 40 mTorr.

[0396] In this case, if the sacrifice oxide layer 63 is left on theinsulating adhesive layer 62, such sacrifice oxide layer 63 as well asthe SiO₂ layer 57 is removed.

[0397] Then, the TiN layer 56 of the second hard mask 58 is removed bythe wet etching using a mixed chemical consisting of hydrogen peroxideand ammonia.

[0398] Then, in order to recover the damage of the ferroelectric layer15 caused by the etching that is executed to form the capacitors Q, therecovery annealing of the capacitors Q is executed. The recoveryannealing in this case is executed at the substrate temperature of 650°C. for 60 min in the atmosphere containing the oxygen, for example.

[0399] Then, like the second embodiment, steps goes to the steps offorming the insulating capacitor protection layer 18, the secondinterlayer insulating layer 19, the fourth conductive plug 21, etc., buttheir details will be omitted herein.

[0400] In the above embodiments, the island-like oxygen barrier metallayer 11 b and the overlying first hard mask 60 a are covered with thealumina-oxidation preventing insulating layer 62. Then, the first hardmask 60 a is removed at the same time when the alumina-oxidationpreventing insulating layer 62 is planarized by the CMP method.Therefore, like the eighth embodiment, there is no necessity toindependently provide the step of removing the first hard mask 60 a.

[0401] Also, the alumina layer has two times an oxidation preventingfunction in contrast to the SiON layer. Thus, in order to prevent theoxidation of the second and third conductive plugs 10 b, 10 c at thetime of oxygen annealing after the formation of the island-likeoxygen-barrier metal layer 11 b, a thickness of the alumina-oxidationpreventing insulating layer 62 may be thinned such as about 50 nm.

[0402] The selective etching ratio of the SiO₂ layer to the aluminalayer is about 40. Hence, an etching depth of the alumina-oxidationpreventing insulating layer 62 generated when the SiO₂ layer 57 of thesecond hard mask 58 is removed by the etching is about 18 to 25 nm.Also, an etching depth of the alumina-oxidation preventing insulatinglayer 62 generated by the overetching after the patterning of thecapacitors Q is about 12 to 17 nm.

[0403] The thickness of the alumina-oxidation preventing insulatinglayer 62 may be set to about 100 nm or more with regard to these etchingamounts. Therefore, if the alumina-oxidation preventing insulating layer62 is planarized by the CMP method, the thickness of the oxygen barriermetal layer 11 b serving as the stopper can be reduced to about 200 nm.As a result, if the distance between the island-like oxygen-barriermetal layers 11 b is narrowed, an increase in the aspect ratio of thespace between the oxygen-barrier metal layers 11 b can be prevented.Thus, the alumina-oxidation preventing insulating layer 62 formed in thespace can be perfectly buried.

[0404] Because no clearance is generated in the alumina-oxidationpreventing insulating layer 62 in such space, no recess is formed in thefirst interlayer insulating layer 8 under the space between theisland-like oxygen barrier metal layers 11 b. Thus, the oxidation of thefirst to third conductive plugs 10 a to 10 c through the firstinterlayer insulating layer 8 can be prevented.

[0405] Also, in order to prevent the oxidation of the second and thirdconductive plugs 10 b, 10 c caused by the crystallization annealing ofthe ferroelectric layer 15 and the recovery annealing after theformation of the capacitors Q, the thickness of the Ir layerconstituting the oxygen-barrier metal layer 11 b together with thethickness of the Ir layer 14 w constituting the lower electrode 14 a ofthe capacitor Q may be set to 300 nm or more. In addition, such layerthickness may be increased further more to meet with the oxidizingannealing temperature after the patterning of the oxygen-barrier metallayer 11 b.

[0406] By the way, in the present embodiment, the thickness of the Irlayer constituting the island-like oxygen-barrier metal layer 11 b isset to 200 nm with regard to the thickness of the Ir layer 14 w of thelower electrode 14 a. If the hard mask is formed as the single-layerstructure of the TiN layer, there is no trouble to pattern such Ir layerhaving the thickness of 200 nm.

[0407] In this case, the above oxidation preventing insulating layer 62has the alumina single-layer structure. But the double-layered structureconsisting of SiO₂ layer and the alumina layer or the double-layeredstructure consisting of the SiON layer and the alumina layer may beemployed.

[0408] (Other Embodiment)

[0409] In the above embodiments, doped silicon may be employed as thematerial of the conductive plug.

[0410] Also, the ferroelectric material is employed as the dielectriclayer of the capacitor, but the high-dielectric material may also beemployed. In addition, the memory cell is explained in the aboveembodiments. Further, as explained in the first, second, and fifthembodiments, in the peripheral circuit or the logic circuit formed onthe semiconductor substrate, the step of forming theoxidation-preventing insulating layer on the first-layer conductive plugmay be contained. In this case, in the peripheral circuit or the logiccircuit, the structure on the impurity diffusion region may be formed asthe structure that connects the conductive plug formed in the contacthole in the first interlayer insulating layer 8 and the conductive plugformed in the contact hole in the oxidation-preventing insulating layer12 and the second interlayer insulating layer 19, like the structure onthe first n-type impurity diffusion region 5 a. The impurity diffusionregions are the source/drain regions of the MOS transistor, for example.

[0411] Also, as explained in the third, fourth, and seventh embodiments,in the peripheral circuit or the logic circuit, the structure on theimpurity diffusion regions constituting the MOS transistor may be formedas the structure that connects sequentially the conductive plug formedin the contact hole in the first interlayer insulating layer 8 and theconductive plug formed, the island-like oxygen-barrier metal layerformed on the first interlayer insulating layer, and the conductive plugformed in the second interlayer insulating layer.

[0412] In addition, ruthenium may be employed as the oxygen-barriermetal layer in place of iridium. Also, the oxygen-barrier metal layermay be formed of a ruthenium lower layer and a ruthenium oxide upperlayer.

[0413] As described above, according to the present invention, the firstand second conductive plugs are formed in the first insulating layer,then the oxygen-barrier metal layer is formed on the first conductiveplug and the oxidation-preventing insulating layer is formed on thesecond conductive plug, then the capacitors are formed on the firstconductive plug via the oxygen-barrier metal layer, then the secondinsulating layer for covering the capacitors is formed, and then thethird conductive plug is formed on the second conductive plug.Therefore, the structure for connecting the impurity diffusion regionand the upper wiring is made on a via-to-via basis, and it is not neededto form the holes having the large aspect ratio at a time, and thefilling of the holes can be facilitated. As a result, the up-to-dateequipment is not required, and the development cost and the step costcan be reduced. Also, the abnormal oxidation of the first conductiveplug can be prevented by the oxygen-barrier metal layer, and also theabnormal oxidation of the second conductive plug can be prevented by theoxidation-preventing insulating layer.

[0414] In addition, since the oxygen-barrier metal layer and theinsulating adhesion layer are planarized simultaneously by thepolishing, the capacitor lower electrode formed on the oxygen-barriermetal layer can be formed flat. Thus, generation of the degradation ofthe dielectric layer formed on the lower electrode can be avoided, andalso formation of the capacitors with good characteristics can beformed.

[0415] Further, by adopting the oxygen-barrier metal layer formed as themulti-layered structure and the upper layer is formed of the materialthat can be relatively easily polished, e.g., iridium oxide, theunderlying layer of the capacitors can be formed flatter by polishingthe insulating adhesion layer and the oxygen-barrier metal layer. Thus,the characteristics of the capacitors can be improved.

[0416] Furthermore, according to the present invention, theoxygen-barrier metal layer instead of the oxidation-preventinginsulating layer is formed like the island on the second conductiveplug. Therefore, not only the same advantages as theoxidation-preventing insulating layer can be obtained but also the stepof forming the oxidation-preventing insulating layer can be omitted.

[0417] In this case, by adopting the oxygen-barrier metal layer formedon the first conductive plug immediately under the capacitor as thelower electrode, the step of patterning the lower electrode can bereduced.

[0418] In the condition of which the conductive adhesion layer is formedbetween the conductive layer constituting the capacitor lower electrodeand the oxygen-barrier metal layer, the peeling-off of the capacitorlower electrode can be prevented without fail.

[0419] By adopting the conductive adhesion layer formed between theoxygen-barrier metal layer and the first insulating layer, the adherencebetween the oxygen-barrier metal layer and the first insulating layercan be improved. Therefore, the oxygen can be prevented without failfrom being supplied from the clearance between the oxygen-barrier metallayer and the first insulating layer to the conductive plug, and thusthe oxidation of the conductive plug can be prevented.

[0420] In the case that the oxygen-barrier metal layer is patterned byusing the hard masks, the insulating adhesion layer is formed on thehard masks and the oxidation-preventing insulating layer after thepatterning of the oxygen-barrier metal layer, and then the insulatingadhesion layer and the hard masks are polished continuously until theoxygen-barrier metal layer is exposed. Therefore, the independent stepof removing the hard masks can be omitted and thus throughput can beimproved.

What is claimed is:
 1. A semiconductor device comprising: a firstimpurity diffusion region and a second impurity diffusion region formedin a surface region of a semiconductor substrate; a first insulatinglayer formed over the semiconductor substrate; a first hole and a secondhole formed in the first insulating layer; a first conductive plugformed in the first hole and connected electrically to the firstimpurity diffusion region; a second conductive plug formed in the secondhole and connected electrically to the second impurity diffusion region;an oxygen-barrier metal layer formed in a shape of an island on thefirst conductive plug and its peripheral area and on the firstinsulating layer; an oxidation preventing layer formed on the firstinsulating layer and made of material that prevents oxidation of thesecond conductive plug; a capacitor having a lower electrode formed onthe oxygen-barrier metal layer, a dielectric layer formed on the lowerelectrode, and an upper electrode formed on the dielectric layer; asecond insulating layer covering the capacitor and the oxidationpreventing layer; a third hole formed in the second insulating layerover the second conductive plug; and a third conductive plug formed inthe third hole and connected electrically to the second conductive plug.2. A semiconductor device according to claim 1, wherein the oxidationpreventing layer is an oxidation preventing insulating layer that isformed on the first insulating layer to cover side surfaces of theoxygen-barrier metal layer, and the third conductive plug is connectedto the second conductive plug.
 3. A semiconductor device according toclaim 2, wherein the oxidation preventing insulating layer consists ofone of alumina, silicon nitride, and silicon oxide nitride.
 4. Asemiconductor device according to claim 2, wherein an upper surface ofthe oxygen-barrier metal layer and an upper surface of the oxidationpreventing insulating layer are planarized under the lower electrode. 5.A semiconductor device according to claim 2, wherein an insulatingadhesion layer is formed on the oxidation preventing insulating layerand under the lower electrode.
 6. A semiconductor device according toclaim 1, wherein the oxidation preventing layer is an island-likeconductive layer formed on the second conductive plug and formed of sameconductive material as the oxygen-barrier metal layer, and the thirdconductive plug is connected to the second conductive plug via theisland-like conductive layer.
 7. A semiconductor device according toclaim 6, wherein an oxidation preventing insulating layer is formed onside surfaces of the island-like conductive layer, side surfaces of theoxygen-barrier metal layer, and an upper surface of the first insulatinglayer.
 8. A semiconductor device according to claim 1, wherein theoxygen-barrier metal layer constitutes a lower layer portion of thelower electrode of the capacitor.
 9. A semiconductor device according toclaim 1, wherein the oxygen-barrier metal layer has a substantially samesize as the lower electrode of the capacitor.
 10. A semiconductor deviceaccording to claim 1, wherein an insulating adhesion layer is formedaround the oxygen-barrier metal layer under the capacitor.
 11. Asemiconductor device according to claim 1, wherein the lower electrodeconsists of conductive layers, and a lowermost layer of the conductivelayers is formed of same material as the oxygen-barrier metal layer, anda total thickness of the lowermost layer and the oxygen-barrier metallayer is set to prevent oxidation of the first conductive plug at anannealing temperature of the dielectric layer.
 12. A semiconductordevice according to claim 1, wherein the oxygen-barrier metal layerconsists of conductive layers, and an uppermost layer of the conductivelayers is formed of conductive material that is polished more easilythan the lowermost layer of the conductive layers.
 13. A semiconductordevice according to claim 1, wherein a conductive adhesion layer isformed between the oxygen-barrier metal layer and the lower electrode.14. A semiconductor device according to claim 13, wherein an uppersurface of the conductive adhesion layer has a same shape as a lowersurface of the lower electrode.
 15. A semiconductor device according toclaim 13, wherein the oxygen-barrier metal layer is formed of samematerial as the conductive adhesion layer, and the conductive adhesionlayer is formed at a position higher than the oxidation preventinginsulating layer.
 16. A semiconductor device according to claim 13,wherein the conductive adhesion layer is formed of iridium.
 17. Asemiconductor device according to claim 1, wherein a conductive adhesionlayer is formed under the oxygen-barrier metal layer and on the firstinsulating layer over the first conductive plug and a peripheral area ofthe first conductive plug.
 18. A semiconductor device according to claim17, wherein the conductive adhesion layer is formed by either asingle-layer structure made of titanium or titanium nitride or adouble-layered structure constructed by forming titanium and titaniumnitride sequentially.
 19. A semiconductor device according to claim 1,wherein the first conductive plug and the second conductive plug containtungsten respectively.
 20. A semiconductor device according to claim 1,wherein the first impurity diffusion region and the second impuritydiffusion region constitute a transistor.
 21. A manufacturing method ofa semiconductor device comprising the steps of: forming a first impuritydiffusion region and a second impurity diffusion region on a surfaceregion of a semiconductor substrate; forming a first insulating layerover the semiconductor substrate; forming a first hole and a second holein the first insulating layer; forming a first conductive plug, which isconnected electrically to the first impurity diffusion region, in thefirst hole and simultaneously forming a second conductive plug, which isconnected electrically to the second impurity diffusion region, in thesecond hole; forming an oxygen-barrier metal layer on the firstconductive plug and on the second conductive plug and over the firstinsulating layer; patterning the oxygen-barrier metal layer to leave theoxygen-barrier metal layer like an island on the first conductive plug;forming an oxidation preventing insulating layer on the secondconductive plug and over the first insulating layer; exposing an uppersurface of the oxygen-barrier metal layer like the island by polishingthe oxidation preventing insulating layer; forming a first conductivelayer on the oxygen-barrier metal layer like the island and over theoxidation preventing insulating layer; forming a dielectric layer on thefirst conductive layer; forming a second conductive layer on thedielectric layer; forming a capacitor on the oxygen-barrier metal layerover the first conductive plug by patterning the second conductivelayer, the dielectric layer, and the first conductive layer; forming asecond insulating layer over the capacitor, and the oxidation preventinginsulating layer; forming a third hole over the second conductive plugby patterning the second insulating layer; and forming a thirdconductive plug, which is connected electrically to the secondconductive plug, in the third hole.
 22. A manufacturing method of asemiconductor device according to claim 21, further comprising the stepsof: forming an insulating adhesion layer over the oxidation preventinginsulating layer, planarizing the insulating adhesion layer and theoxidation preventing insulating layer at the same time; and forming thethird hole also in the insulating adhesion layer.
 23. A manufacturingmethod of a semiconductor device according to claim 21, furthercomprising the steps of: patterning the oxygen-barrier metal layer toleave the oxygen-barrier metal layer as an oxidation preventingconductive layer like an island on the second conductive plug andperipheral area of the second conductive plug; forming the third hole onthe oxidation preventing conductive layer made of the oxygen-barriermetal layer; and forming the third conductive plug in the third hole tobe connected to the second conductive plug electrically via theoxidation preventing conductive layer.
 24. A manufacturing method of asemiconductor device according to claim 21, wherein the oxygen-barriermetal layer is patterned as a part of the lower electrode of thecapacitor.
 25. A manufacturing method of a semiconductor deviceaccording to claim 21, wherein the oxygen-barrier metal layer ispatterned to have a substantially same size as the lower electrode ofthe capacitor.
 26. A manufacturing method of a semiconductor deviceaccording to claim 21, wherein the oxygen-barrier metal layer consistsof a lower layer and an upper layer, both made of different material,and the upper layer is made of a second material that is polished moreeasily than a first material constituting the lower layer.
 27. Amanufacturing method of a semiconductor device according to claim 21,further comprising the steps of: forming a conductive adhesion layerbetween the oxygen-barrier metal layer like island and the firstconductive layer; and patterning the conductive adhesion layer togetherwith the first conductive layer into an island shape.
 28. Amanufacturing method of a semiconductor device according to claim 21,further comprising the steps of: forming a conductive adhesion layerbetween the oxygen-barrier metal layer and the first insulating layer;and patterning the conductive adhesion layer together with theoxygen-barrier metal layer into the island shape.
 29. A manufacturingmethod of a semiconductor device according to claim 21, furthercomprising the steps of: forming a hard mask on the oxygen-barrier metallayer and over the first conductive plug; and etching a part of theoxygen-barrier metal layer exposed from the hard mask to leave theoxygen-barrier metal layer like the island.
 30. A manufacturing methodof a semiconductor device according to claim 21, further comprising thesteps of: removing the hard mask to expose the upper surface of theoxygen-barrier metal layer like the island by polishing, after coveringthe hard mask with the oxidation preventing insulating layer.
 31. Amanufacturing method of a semiconductor device according to claim 30,wherein the hard mask is formed of same material as materialconstituting a part of the second conductive plug.
 32. A manufacturingmethod of a semiconductor device according to claim 30, wherein an upperportion of the hard mask consists of silicon oxidation.
 33. Amanufacturing method of a semiconductor device according to claim 30,wherein the oxidation preventing insulating layer consists of one of asingle layer of alumina and a plural layer having alumina.